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PE43205MLAA-Z Arkusz danych(PDF) 5 Page - Peregrine Semiconductor |
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PE43205MLAA-Z Arkusz danych(HTML) 5 Page - Peregrine Semiconductor |
5 / 11 page Product Specification PE43205 Page 5 of 11 Document No. DOC-30914-3 │ www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved. 15.0 17.0 19.0 21.0 23.0 25.0 27.0 29.0 35 350 3500 Frequency (MHz) Maximum Input Power RF Input Power, Pulsed @ 25C Ambient RF Input Power, Pulsed @ 105C Ambient RF Input Power, CW @ 25C Ambient RF Input Power, CW @ 105C Ambient Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Table 5. Attenuation Word Truth Table C1 C2 Attenuation Setting RF1–RF2 L L Reference I.L. H L 6 dB L H 12 dB H H 18 dB Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE43205 in the 12-lead 3x3 mm QFN package is MSL1. Switching Frequency The PE43205 has a maximum 25 kHz switching rate. Switching rate is defined to be the speed at which the DSA can be toggled across attenuation states. Switching time is the time duration between the point the control signal reaches 50% of the final value and the point the output signal reaches within 10% or 90% of its target value. Spurious Performance The typical low-frequency spurious performance of the PE43205 is –135 dBm. Figure 4. Power De-Rating Curve for 35 MHz–4 GHz |
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