 |
Zakładka z wyszukiwarką danych komponentów |
|
|
Zakładka z wyszukiwarką danych komponentów |
|
AD5328 Arkusz danych(PDF) 11 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
AD5328 Arkusz danych(HTML) 11 Page - Analog Devices |
|
|
11 / 19 page  REV. B AD5308/AD5318/AD5328 –11– FUNCTIONAL DESCRIPTION The AD5308/AD5318/AD5328 are octal resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10, and 12 bits, respectively. Each contains eight output buffer amplifiers and is written to via a 3-wire serial interface. They operate from single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/ µs. DACs A, B, C, and D share a common reference input, VREFABCD. DACs E, F, G, and H share a common reference input, VREFEFGH. Each reference input may be buffered to draw virtually no current from the reference source, may be unbuffered to give a reference input range from 0.25 V to VDD, or may come from VDD. The devices have a power- down mode in which all DACs may be turned off individually with a high impedance output. Digital-to-Analog Section The architecture of one DAC channel consists of a resistor- string DAC followed by an output buffer amplifier. The voltage at the VREF pin provides the reference voltage for the corre- sponding DAC. Figure 4 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by V VD OUT REF N = × 2 where D = decimal equivalent of the binary code that is loaded to the DAC register: 0–255 for AD5308 (8 bits) 0–1023 for AD5318 (10 bits) 0–4095 for AD5328 (12 bits) N = DAC resolution VOUTA GAIN MODE (GAIN = 1 OR 2) VREFABCD BUF DAC REGISTER INPUT REGISTER RESISTOR STRING OUTPUT BUFFER AMPLIFIER REFERENCE BUFFER VDD VDD Figure 4. Single DAC Channel Architecture Resistor String The resistor-string section is shown in Figure 5. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. TO OUTPUT AMPLIFIER R R R R R Figure 5. Resistor String DAC Reference Inputs There is a reference pin for each quad of DACs. The reference inputs can be buffered from VDD, or unbuffered. The advantage with the buffered input is the high impedance it presents to the voltage source driving it. However, if the unbuffered mode is used, the user can have a reference voltage as low as 0.25 V and as high as VDD since there is no restriction due to the headroom and footroom of the reference amplifier. If there is a buffered reference in the circuit (e.g., REF192), there is no need to use the on-chip buffers of the AD5308/AD5318/ AD5328. In unbuffered mode, the input impedance is still large at typically 45 k Ω per reference input for 0 V to VREF mode and 22 k Ω for 0 V to 2 V REF mode. Output Amplifier The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends on the value of VREF, the gain of the output amplifier, the offset error, and the gain error. If a gain of 1 is selected (GAIN bit = 0), the output range is 0.001 V to VREF. If a gain of 2 is selected (GAIN bit = 1), the output range is 0.001 V to 2 VREF. Because of clamping, however, the maxi- mum output is limited to VDD – 0.001 V. The output amplifier is capable of driving a load of 2 k Ω to GND or VDD, in parallel with 500 pF to GND or VDD. The source and sink capabilities of the output amplifier can be seen in the plot in TPC 11. The slew rate is 0.7 V/ µs with a half-scale settling time to ±0.5 LSB (at eight bits) of 6 µs. POWER-ON RESET The AD5308/AD5318/AD5328 are provided with a power-on reset function so that they power up in a defined state. The power-on state is • Normal operation • Reference inputs unbuffered • 0 V to VREF output range • Output voltage set to 0 V • LDAC bits set to LDAC high Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up. |
Podobny numer części - AD5328 |
|
Podobny opis - AD5328 |
|
|
|
Link URL |
| Polityka prywatności |
| ALLDATASHEET.PL |
| Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Polish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
