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TP3070V Arkusz danych(PDF) 7 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numer części TP3070V
Szczegółowy opis  COMBO II Programmable PCM CODEC/Filter
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Producent  NSC [National Semiconductor (TI)]
Strona internetowa  http://www.national.com
Logo NSC - National Semiconductor (TI)

TP3070V Arkusz danych(HTML) 7 Page - National Semiconductor (TI)

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Programmable Functions (Continued)
TABLE 5. Coding Law Conventions
µ255 law
True A-law with
A-law without
even bit inversion
even bit inversion
MSB
LSB
MSB
LSB
MSB
LSB
V
IN = +Full Scale
10000000
10101010
11111111
V
IN = 0V
11111111
11010101
10000000
01111111
01010101
00000000
V
IN = −Full Scale
00000000
00101010
01111111
Note 5: The MSB is always the first PCM bit shifted in or out of COMBO II.
TABLE 6. Time-Slot and Port Assignment Instruction
Bit Number and Name
Function
7
6
5
43210
EN
PS
T
5
T
4
T
3
T
2
T
1
T
0
(Note 6)
(Note 7)
0
0
X
XXXXX
Disable D
X0 Output (Transmit Instruction)
Disable D
R0 Input (Receive Instruction)
0
1
X
XXXXX
Disable D
X1 Output (Transmit Instruction)
Disable D
R1 Input (Receive Instruction)
1
0
Assign One Binary Coded Time-Slot from 0–63
Enable D
X0 Output (Transmit Instruction)
Assign One Binary Coded Time-Slot from 0–63
Enable D
R0 Input (Receive Instruction)
1
1
Assign One Binary Coded Time-Slot from 0–63
Enable D
X1 Output (Transmit Instruction)
Assign One Binary Coded Time-Slot from 0–63
Enable D
R1 Input (Receive Instruction)
Note 6: The “PS” bit MUST always be set to 0 for the TP3071.
Note 7: T5 is the MSB of the Time-slot assignment bit field. Time slot bits should be set to “000000” for both transmit and receive when operating in non-delayed
data timing mode.
5.0 TIME-SLOT ASSIGNMENT
COMBO II can operate in either fixed time-slot or time-slot
assignment mode for selecting the Transmit and Receive
PCM time-slots. Following power-on, the device is automati-
cally in Non-Delayed Timing mode, in which the time-slot al-
ways begins with the leading (rising) edge of frame sync in-
puts FS
X and FSR. Time-Slot Assignment may only be used
with Delayed Data timing; see
Figure 5.FS
X and FSR may
have any phase relationship with each other in BCLK period
increments.
Alternatively, the internal time-slot assignment counters and
comparators can be used to access any time-slot in a frame,
using the frame sync inputs as marker pulses for the begin-
ning of transmit and receive time-slot 0. In this mode, a
frame may consist of up to 64 time-slots of 8 bits each. A
time-slot is assigned by a 2-byte instruction as shown in
Table 1 and Table 6. The last 6 bits of the second byte indi-
cate the selected time-slot from 0–63 using straight binary
notation. When writing a timeslot and port assignment regis-
ter, if the PCM interface is currently active, it is immediately
deactivated to prevent possible bus clashes. A new assign-
ment becomes active on the second frame following the end
of the Chip-Select for the second control byte. Rewriting of
register contents should not be performed during the talking
period of a connection to prevent waveform distortion
caused by loss of a sample which will occur with each regis-
ter write. The “EN” bit allows the PCM inputs, D
R0/1, or out-
puts, D
X0/1, as appropriate, to be enabled or disabled.
Time-Slot Assignment mode requires that the FS
X and FSR
pulses must conform to the delayed data timing format
shown in
Figure 5.
6.0 PORT SELECTION
On the TP3070 only, an additional capability is available; 2
Transmit serial PCM ports, D
X0 and DX1, and 2 Receive se-
rial PCM ports, D
R0
and D
R1,
are provided to enable
two-way space switching to be implemented. Port selections
for transmit and receive are made within the appropriate
time-slot assignment instruction using the “PS” bit in the sec-
ond byte. The PS bit selects either Port 0 or Port 1. Both
ports cannot be active at the same time.
On the TP3071, only ports D
X0 and DR0 are available, there-
fore the “PS” bit MUST always be set to 0 for these devices.
Table 6 shows the format for the second byte of both trans-
mit and receive time-slot and port assignment instructions.
7.0 TRANSMIT GAIN INSTRUCTION BYTE 2
The transmit gain can be programmed in 0.1 dB steps by
writing to the Transmit Gain Register as defined in
Table 1
and
Table 7. This corresponds to a range of 0 dBm0 levels at
VF
XI between 1.619 Vrms and 0.087 Vrms (equivalent to
+6.4 dBm to −19.0 dBm in 600
Ω).
To calculate the binary code for byte 2 of this instruction for
any desired input 0 dBm0 level in Vrms, take the nearest in-
teger to the decimal number given by:
200 x log
10 (V/0.08595)
www.national.com
7


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