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TP3406 Arkusz danych(PDF) 5 Page - National Semiconductor (TI) |
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TP3406 Arkusz danych(HTML) 5 Page - National Semiconductor (TI) |
5 / 16 page Functional Description (Continued) BURST MODE OPERATION For full-duplex operation over a single twisted-pair burst mode timing is used with the line-card (exchange) end of the link acting as the timing Master Each burst from the Master consists of the B1 B2 and D channel data from 2 consecutive frames combined in the format shown in Figure 5 During transmit bursts the Mas- ter’s receiver input is inhibited to avoid disturbing the adap- tive circuits The Slave’s receiver is enabled at this time and it synchronizes to the start bit of the burst which is always an unscrambled ‘1’ (of the opposite polarity to the last ‘1’ sent in the previous burst) When the Slave detects that 36 bits following the start bit have been received it disables the receiver input waits 6 line symbol periods to match the oth- er end settling guard time and then begins to transmit its burst back towards the Master which by this time has en- abled its receiver input The burst repetition rate is thus 4 kHz which can either free-run or be locked to a synchro- nizing signal at the Master end by means of the MBS input (See Figure 10 ) In the latter case with all Master-end transmitters in a system synchronized together near-end crosstalk between pairs in the same cable binder may be eliminated with a consequent increase in signal-to-noise ra- tio (SNR) ACTIVATION AND LOOP SYNCHRONIZATION Activation (ie power-up and loop synchronization) is typi- cally completed in 50 ms and may be initiated from either end of the loop If the Master is activating the loop it sends normal bursts of scrambled ‘1’s which are detected by the Slave’s line-signal detect circuit causing it to set C0 e 1in the Status Register and pull the INT pin low Pin 6 the LSD pin also pulls low To proceed with Activation the device must be powered up by writing to the Control Register with C6 e 1 The Slave then replies with bursts of scrambled ‘1’s synchronized to received bursts and the flywheel circuit at each end searches for 4 consecutive correctly formatted receive bursts to acquire full loop synchronization Each re- ceiver indicates when it is correctly in sync with received bursts by setting the C1 bit in the Status Register high and pulling INT low To activate the loop from the Slave end bit C6 in the Con- trol Register must be set high which will power-up the de- vice and begin transmission of alternate bursts ie the burst repetition rate is 2 kHz not 4 kHz At this point the Slave is running from its local oscillator and is not receiving any sync information from the Master When the Master’s line-signal detect circuit recognizes this ‘‘wake-up’’ signal the Master is activated and begins to transmit bursts synchronized as normal to the MBS or FSa input with a 4 kHz repetition rate This enables the Slave’s receiver to correctly identify burst timing from the Master and to re-synchronize its own burst transmissions to those it receives The flywheel circuits then acquire full loop sync as described earlier Loop synchronization is considered to be lost if the flywheel finds 4 consecutive receive burst ‘‘windows’’ (ie where a receive burst should have arrived based on timing from pre- vious bursts) do not contain valid bursts At this point bit C1 in the Status Register is set low the INT output is set low and the receiver searches to re-acquire loop sync DIGITAL SYSTEM INTERFACE The digital system interface on the DASL separates B and D channel information onto different pins to provide maximum flexibility On the B channel interface phase skew between transmit and receive directions may be accommodated at the Master end since separate frame sync inputs Fsa and Fsb are provided Each of these synchronizes a counter which gates the transfer of B1 and B2 channels in consecu- tive time-slots across the digital interface since the coun- ters are edge-synchronized the duration of the Fs input sig- nals may vary from a single-bit pulse to a square-wave The serial shift rate is determined by the BCLK input and may be any frequency from 256 kHz to 2048 MHz as shown in Figure 6 At the Slave end both Fsa and Fsb are outputs Fsa goes high for 8 cycles of BCLK coincident with the 8 bits of the B1 channel in both Transmit and Receive directions Fsb goes high for the next 8 cycles of BCLK which are coinci- dent with the 8 bits of the B2 channel in both Transmit and Receive directions BCLK is also an output at 2048 MHz the serial data shift rate as shown in Figure 7 Data may be exchanged between the B1 and B2 channels as it passes through the device by setting Control bit C0 e 1 An addi- tional Frame Sync output FSc is provided to enable a re- generator to be built by connecting a DASL in Slave Mode to a DASL in Master Mode The FSc output from the Slave directly drives the FSa and FSb inputs on the Master D channel information being packet-mode requires no syn- chronizing input This interface consists of the transmit data input Dx receive data output Dr and 16 kHz serial shift clock DCLK which is an input at the Master end and an output at the Slave end Data shifts into Dx on falling edges of DCLK and out from Dr on rising edges as shown in Fig- ure 11 DCLK should be Synchronous with BCLK An alternative function of the DCLKDEN pin allows Dx and Dr to be clocked at the same rate as BCLK at the Master end only By setting bit C1 in the Control Register to a 1 DCLKDEN becomes an input for an enabling pulse to gate 2 cycles of BCLK for shifting the 2 D bits per frame Thus at the Master end the D channel bits can be interfaced to a TDM bus and assigned to a time-slot (the same time-slot for both transmit and receive) as shown in Figure 12 CONTROL INTERFACE A serial interface which can be clocked independently from the B and D channel system interfaces is provided for mi- croprocessor control of various functions on the DASL de- vice All data transfers consist of a single byte shifted into the Control Register via CI simultaneous with a single byte shifted out from the Status Register via CO see Figure 13 Data shifts in to CI on rising edges of CCLK and out from CO on falling edges when CS is pulled low for 8 cycles of CCLK An Interrupt output INT goes low to alert the micro- processor whenever a change in one of the status bits C1 andor C0 has occurred This latched output is cleared high following the first CCLK pulse when CS is low No interrupt is generated when status bit C2 (bipolar violation) goes high however This bit is set whenever 1 or more violations of the AMI coding rule is received and cleared everytime the CS is pulsed Statistics on the line bit error rate can be accumulat- ed by regularly polling this bit When reading the CO pin data is always clocked into the Control Register therefore the CI data word should repeat the previous instruction if no change to the device mode is intended Figure 13 shows the timing for this interface and Table II lists the control functions and status indicators 5 |
Podobny numer części - TP3406 |
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Podobny opis - TP3406 |
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