Zakładka z wyszukiwarką danych komponentów |
|
TP3071AN-G Arkusz danych(PDF) 6 Page - National Semiconductor (TI) |
|
|
TP3071AN-G Arkusz danych(HTML) 6 Page - National Semiconductor (TI) |
6 / 26 page Programmable Functions (Continued) vice is powered-up or down by setting the “P” bit as indi- cated. When the power-up or down control is entered as a single byte instruction, bit one (1) must be reset to a 0. When a power-up command is given, all de-activated circuits are activated, but the TRI-STATE PCM output(s), D X0 (and D X1), will remain in the high impedance state until the sec- ond FS X pulse after power-up. 2.0 CONTROL REGISTER INSTRUCTION The first byte of a READ or WRITE instruction to the Control Register is as shown in Table 1. The second byte has the fol- lowing bit functions: TABLE 2. Control Register Byte 2 Functions Bit Number and Name 76 5 43210 Function F1 F0 MA IA DN DL AL PP 0 0 MCLK = 512 kHz 0 1 MCLK = 1.536 or 1.544 MHz 1 0 MCLK = 2.048 MHz (Note 4) 1 1 MCLK = 4.096 MHz 0 X Select µ-255 law (Note 4) 1 0 A-law, Including Even Bit Inversion 1 1 A-law, No Even Bit Inversion 0 Delayed Data Timing 1 Non-Delayed Data Timing (Note 4) 0 0 Normal Operation (Note 4) 1 X Digital Loopback 0 1 Analog Loopback 0 Power Amp Enabled in PDN 1 Power Amp Disabled in PDN (Note 4) Note 4: State at power-on initialization. (Bit 4 = 0) 2.1 Master Clock Frequency Selection A Master clock must be provided to COMBO II for operation of the filter and coding/decoding functions. The MCLK fre- quency must be either 512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or 4.096 MHz and must be synchronous with BCLK. Bits F 1 and F0 (see Table 2) must be set during initial- ization to select the correct internal divider. 2.2 Coding Law Selection Bits “MA” and “IA” in Table 2 permit the selection of µ255 coding or A-law coding, with or without even bit inversion. 2.3 Analog Loopback Analog Loopback mode is entered by setting the “AL” and “DL” bits in the Control Register as shown in Table 2.Inthe analog loopback mode, the Transmit input VF XI is isolated from the input pin and internally connected to the VF RO out- put, forming a loop from the Receive PCM Register back to the Transmit PCM Register. The VF RO pin remains active, and the programmed settings of the Transmit and Receive gains remain unchanged, thus care must be taken to ensure that overload levels are not exceeded anywhere in the loop. Hybrid balance must be disabled for meaningful analog loop- back function. 2.4 Digital Loopback Digital Loopback mode is entered by setting the “AL” and “DL” bits in the Control Register as shown in Table 2. This mode provides another stage of path verification by enabling data written into the Receive PCM Register to be read back from that register in any Transmit time-slot at D X0/1. In digital loopback, the decoder will remain functional and output a signal at VF RO. If this is undesirable, the receive output can be turned off by programming the receive gain register to all zeros. 3.0 INTERFACE LATCH DIRECTIONS Immediately following power-on, all Interface Latches as- sume they are inputs, and therefore all IL pins are in a high impedance state. Each IL pin may be individually pro- grammed as a logic input or output by writing the appropriate instruction to the LDR, see Table 1 and Table 3. For mini- mum power dissipation, unconnected latch pins should be programmed as outputs. For the TP3071, L5 should always be programmed as an output. Bits L 5–L0 must be set by writing the specified instruction to the LDR with the L bits in the second byte set as follows: TABLE 3. Byte 2 Functions of Latch Direction Register Byte 2 Bit Number 765432 1 0 L 0 L 1 L 2 L 3 L 4 L 5 XX L n Bit IL Direction 0 Input 1 Output X = don’t care INTERFACE LATCH STATES Interface Latches configured as outputs assume the state determined by the appropriate data bit in the 2-byte instruc- tion written to the Interface Latch Register (ILR) as shown in Table 1 and Table 4. Latches configured as inputs will sense the state applied by an external source, such as the Off-Hook detect output of a SLIC. All bits of the ILR, i.e. sensed inputs and the programmed state of outputs, can be read back in the 2nd byte of a READ from the ILR. It is recommended that during initialization, the state of IL pins to be configured as outputs should be programmed first, followed immediately by the Latch Direction Register. TABLE 4. Interface Latch Data Bit Order Bit Number 765432 1 0 D 0 D 1 D 2 D 3 D 4 D 5 XX www.national.com 6 |
Podobny numer części - TP3071AN-G |
|
Podobny opis - TP3071AN-G |
|
|
Link URL |
Polityka prywatności |
ALLDATASHEET.PL |
Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |