Zakładka z wyszukiwarką danych komponentów
  Polish  ▼
ALLDATASHEET.PL

X  

TP3420AJ Arkusz danych(PDF) 7 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numer części TP3420AJ
Szczegółowy opis  ISDN S/T Interface Device
Download  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  NSC [National Semiconductor (TI)]
Strona internetowa  http://www.national.com
Logo NSC - National Semiconductor (TI)

TP3420AJ Arkusz danych(HTML) 7 Page - National Semiconductor (TI)

Back Button TP3420AJ Datasheet HTML 3Page - National Semiconductor (TI) TP3420AJ Datasheet HTML 4Page - National Semiconductor (TI) TP3420AJ Datasheet HTML 5Page - National Semiconductor (TI) TP3420AJ Datasheet HTML 6Page - National Semiconductor (TI) TP3420AJ Datasheet HTML 7Page - National Semiconductor (TI) TP3420AJ Datasheet HTML 8Page - National Semiconductor (TI) TP3420AJ Datasheet HTML 9Page - National Semiconductor (TI) TP3420AJ Datasheet HTML 10Page - National Semiconductor (TI) TP3420AJ Datasheet HTML 11Page - National Semiconductor (TI) Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 32 page
background image
Functional Description (Continued)
DIGITAL SYSTEM INTERFACE
The Digital System Interface (DSI) on the TP3420A com-
bines “B” and “D” channel data onto common pins to provide
maximum flexibility with minimum pin count. Several multi-
plexed formats of the B and D channel data are available as
shown in
Figure 3. Selection is made via the Control Regis-
ter.
NTA, NTF and TES modes: at this interface, phase skew be-
tween transmit and receive frames may be accommodated
when the device is a slave at the Digital Interface (NT and
TES Modes) since separate frame sync inputs (
Figure 3),
FS
a and FSb, are provided. Each of these synchronizes a
counter which gates the transfer of B1 and B2 channels in
consecutive time-slots across the digital interface. The serial
shift rate is determined by the BCLK input, and may be any
multiple of 8 kHz from 256 kHz to 4.096 MHz. Thus, for ap-
plications on a PABX line-card (in NT mode), the “B” and “D”
channel slots can be interfaced to a TDM bus and assigned
to a time-slot.
TEM mode: in TE Master Mode (TEM), FS
a is an output (Fig-
ure 4) indicating the start of both transmit and receive “B”
channel data transfers. BCLK is also an output at the serial
data shift rate, which is dependent on the format selected,
see
Table 5.
TES mode: for applications such as the network side of an
NT-2, e.g. a PBX trunk card, the TE Slave (TES) Mode is
provided. This “slave-slave” mode allows the transmission
side of the device to be a slave to the received frame timing,
while the Digital System Interface is also in a slave mode i.e.
FS
a,FSb and BCLK are inputs. The Digital System Interface
includes elastic buffers which allow any arbitrary phase rela-
tionship between each FS input and the received I.430
frame.
JITTER ABSORPTION AND PHASE WANDER BUFFERS
The TP3420A has an improved serial data buffer circuit to
handle larger amounts of phase wander exceeding the
specification of 18 µs pk-to-pk, regardless of the phase dif-
ference between the transmit and receive frames. A SLIP in-
dicator interrupt is generated to inform the CPU if the phase
deviation between two clocks exceeds the boundary of the
circuit, causing the data buffers to adjust the internal delay to
accommodate this. Under some, but not all, circumstances
this will result in data errors as the slip occurs. Separate in-
terrupt status values (SLIP — TX and SLIP — RX) indicate
the clock slippage in the transmit buffer or the receiver buffer.
TES Mode also provides a synchronized clock output
(SCLK) which is phase-locked to the received line signal;
SCLK may be used as the BCLK source.
TABLE 3. DSI Format Rates
BLCK as
BCLK as
Format
DSI Master
DSI Slave
(Output) (Note 5)
(Input)
1
2.048 MHz
256 kHz–4.096 MHz
2
256 kHz
256 kHz–4.096 MHz
BLCK as
BCLK as
Format
DSI Master
DSI Slave
(Output) (Note 5)
(Input)
3
512 kHz
512 kHz–4.096 MHz
4
2.56 MHz
256 kHz–4.096 MHz
Note 5: also SCLK output in TES Mode.
MICROWIRE CONTROL INTERFACE
A serial interface, which can be clocked independently from
the “B” and “D” channel system interface, is provided for mi-
croprocessor control of various functions in the TP3420. This
port can be used when the device is powered up or powered
down. All data transfers consist of a single byte shifted into
the Control Register via the CI pin, simultaneous with a
single byte shifted out from the Status Register via the CO
pin.
Data shifts in to CI on rising edges of CCLK and out from CO
on falling edges when CS is pulled low for 8 cycles of CCLK.
An Interrupt output, INT goes low to alert the microprocessor
whenever a change occurs in one or more of the conditions
indicated in the Status Register. This latched output is
cleared to a high impedance state by the first rising CCLK
edge after CS goes low. Interrupt Source(s) occurring while
another is still pending are stored in a stack and read in se-
quence, by causing another interrupt at the end of the cur-
rent CS cycle (INT can go low only when CS is high). When
reading the Status Register the CI input is also enabled,
therefore a “dummy” command e.g. NOP(X’FF) must be
loaded into CI as CO is read.
Each source of an Interrupt event (
e.g., EI, AI, SLIP) in the
device has an internal latch, such that the occurrence of that
event is stored until read from the status register. Multiple
events will be reported in turn by the device in a circular
manner. There is no priority criteria. If multiple occurrences
of the same event occur (
e.g., EI, followed by AI and then EI)
and if left unserviced, than the second occurrence (of EI in
this example) will over-write the first. Also if a multiframe in-
terrupt such as MFR1 interrupt is not serviced before a sec-
ond occurrence of the MFR1 interrupt, then the second value
in the M1–M4 bits will overwrite the first. The DI interrupt
clears all pending interrupts and indicating the reset state of
the device. The LSD interrupt is generated independently
and is only valid while the device is in low power mode
(PDN). A PUP command resets the line signal detect circuit
and the LSD interrupt. A PDN command resets and
re-enables the LSD circuit and interrupt.
Figure 5 shows the timing for this interface, and Table 4 and
Table 5 list the control functions and status indicators.
FLEXIBLE MICROWIRE PORT
The MICROWIRE port of the TP3420A has been enhanced
such that it can connect to standard MICROWIRE master
devices (such as National’s microcontrollers of the HPC and
COP families) as well as the SCP interface master from the
Motorola microcontroller family. SCP is the Serial Control
Port on devices such as the MC68302 or the MC145488
HDLC. See the MICROWIRE port timing diagram and the
applications section.
www.national.com
7


Podobny numer części - TP3420AJ

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Texas Instruments
TP3420A TI1-TP3420A Datasheet
568Kb / 34P
[Old version datasheet]   TP3420A ISDN S/T Interface Device
TP3420AV308/NOPB TI1-TP3420AV308/NOPB Datasheet
568Kb / 34P
[Old version datasheet]   TP3420A ISDN S/T Interface Device
logo
National Semiconductor ...
TP3420AV309 NSC-TP3420AV309 Datasheet
84Kb / 3P
   Engineering Project Manager
logo
Texas Instruments
TP3420AV309/63SN TI1-TP3420AV309/63SN Datasheet
568Kb / 34P
[Old version datasheet]   TP3420A ISDN S/T Interface Device
TP3420AV309/NOPB TI1-TP3420AV309/NOPB Datasheet
568Kb / 34P
[Old version datasheet]   TP3420A ISDN S/T Interface Device
More results

Podobny opis - TP3420AJ

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Texas Instruments
TP3420A TI1-TP3420A_11 Datasheet
568Kb / 34P
[Old version datasheet]   TP3420A ISDN S/T Interface Device
logo
National Semiconductor ...
TP3421 NSC-TP3421 Datasheet
816Kb / 18P
   ISDN S / T INTERFACE DEVICE WITH GCI ( GENERAL CIRCUIT INTERFACE )
logo
Motorola, Inc
MC145574 MOTOROLA-MC145574 Datasheet
1Mb / 164P
   ISDN S/T-Interface Transceiver
MC145474 MOTOROLA-MC145474 Datasheet
460Kb / 111P
   ISDN S/T Interface Transceiver
logo
Winbond
W6691 WINBOND-W6691 Datasheet
465Kb / 106P
   ISDN S/T Interface Transceiver
logo
PCA ELECTRONICS INC.
EPR1260 PCA-EPR1260 Datasheet
45Kb / 1P
   ISDN S/T-Interface Module
logo
NXP Semiconductors
MC145574EVK NXP-MC145574EVK Datasheet
234Kb / 2P
   ISDN S/T-interface Transceiver Evaluation Kit
REV 0
logo
Macronix International
MX97102 MCNIX-MX97102 Datasheet
309Kb / 42P
   ISDN S/T CONTROLLER
logo
Winbond
W66910 WINBOND-W66910 Datasheet
689Kb / 81P
   TE Mode ISDN S/T-Controller with Microprocessor Interface
logo
Asahi Kasei Microsystem...
AK520S AKM-AK520S Datasheet
1Mb / 8P
   ISDN SINGLE CHIP NT1/(U&S/T-INTERFACE) TRANSCEIVER
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32


Arkusz danych Pobierz

Go To PDF Page


Link URL




Polityka prywatności
ALLDATASHEET.PL
Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com