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UPD48288209AF1 Arkusz danych(PDF) 15 Page - Renesas Technology Corp |
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UPD48288209AF1 Arkusz danych(HTML) 15 Page - Renesas Technology Corp |
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15 / 54 page  µµµµPD48288209AF1, µµµµPD48288218AF1, µµµµPD48288236AF1 R10DS0254EJ0101 Rev. 1.01 Page 15 of 53 Jan. 15, 2016 AC Characteristics <Read and Write Cycle> Parameter Symbol –E18 –E24 Unit Note (533 MHz) (400 MHz) (300 MHz) MIN. MAX. MIN. MAX. MIN. MAX. Clock Clock cycle time (CK,CK#,DK,DK#) tCK, tDK 1.875 5.7 2.5 5.7 3.3 5.7 ns Clock frequency (CK,CK#,DK,DK#) tCK, tDK 175 533 175 400 175 300 MHz Random Cycle time tRC 15 15 20 ns Clock Jitter: period tJIT PER –100 100 –150 150 –200 200 ps 1, 2 Clock Jitter: cycle-to-cycle tJIT CC 200 300 400 ps Clock HIGH time (CK,CK#,DK,DK#) tCKH, tDKH 0.45 0.55 0.45 0.55 0.45 0.55 Cycle Clock LOW time (CK,CK#,DK,DK#) tCKL, tDKL 0.45 0.55 0.45 0.55 0.45 0.55 Cycle Clock to input data clock tCKDK –0.3 0.3 –0.45 0.5 –0.45 1.0 ns Mode register set cycle time tMRSC 6 6 6 Cycle to any command PLL Lock time tCK Lock 15 15 15 µs Clock static to PLL reset tCK Reset 30 30 30 ns Output Times Output data clock HIGH time tQKH 0.9 1.1 0.9 1.1 0.9 1.1 tCKH Output data clock LOW time tQKL 0.9 1.1 0.9 1.1 0.9 1.1 tCKL QK edge to clock edge skew tCKQK –0.2 0.2 –0.25 0.25 –0.3 0.3 ns QK edge to output data edge tQKQ0, tQKQ1 –0.12 0.12 –0.2 0.2 –0.25 0.25 ns 3, 5 QK edge to any output data tQKQ –0.22 0.22 –0.3 0.3 –0.35 0.35 ns 4, 5 QK edge to QVLD tQKVLD –0.22 0.22 –0.3 0.3 –0.35 0.35 ns Setup Times Address/command and input tAS/tCS 0.3 0.4 0.5 ns Data-in and data mask to DK tDS 0.17 0.225 0.3 ns Hold Times Address/command and input tAH/tCH 0.3 0.4 0.5 ns Data-in and data mask to DK tDH 0.17 0.225 0.3 ns Notes 1. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 2. Frequency drift is not allowed. 3. tQKQ0 is referenced to DQ0–DQ17 in x36 and DQ0–DQ8 in x18. tQKQ1 is referenced to DQ18–DQ35 in x36 and DQ9–DQ17 in x18. 4. tQKQ takes into account the skew between any QKx and any DQ. 5. tQKQ, tQKQX are guaranteed by design. Remark All timing parameters are measured relative to the crossing point of CK/CK#, DK/DK# and to the crossing point with VREF of the command, address, and data signals. |
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