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UPD48576209F1 Arkusz danych(PDF) 12 Page - Renesas Technology Corp |
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UPD48576209F1 Arkusz danych(HTML) 12 Page - Renesas Technology Corp |
12 / 54 page µµµµPD48576209F1, µµµµPD48576218F1, µµµµPD48576236F1 R10DS0256EJ0101 Rev. 1.01 Page 12 of 53 Jan. 15, 2016 DC Characteristics IDD / ISB Operating Conditions Parameter Symbol Test condition MAX. Unit –E18 –E24 tRC=15ns tRC=20ns 533MHz 400MHz 400MHz 300MHz Standby current ISB1 tCK = Idle VDD x9/x18 55 55 55 55 mA All banks idle, no inputs toggling x36 55 55 55 55 VEXT 5 5 5 5 Active standby ISB2 CS# = HIGH, No commands, half bank / address / VDD x9/x18 250 215 215 190 mA current data change once every four clock cycles x36 250 215 215 190 VEXT 5 5 5 5 Operating current IDD1 BL=2, sequential bank access, bank transitions VDD x9/x18 390 331 321 291 mA once every tRC, half address transitions once x36 407 346 336 306 every tRC, read followed by write sequence, VEXT 10 10 10 10 continuous data during WRITE commands. Operating current IDD2 BL=4, sequential bank access, bank transitions VDD x9/x18 422 367 357 336 mA once every tRC, half address transitions once x36 445 387 377 353 every tRC, read followed by write sequence, VEXT 10 10 10 10 continuous data during WRITE commands. Operating current IDD3 BL=8, sequential bank access, bank transitions VDD x9/x18 439 381 371 350 mA once every tRC, half address transitions once x36 488 419 409 388 every tRC, read followed by write sequence, VEXT 15 15 15 15 continuous data during WRITE commands. Burst refresh IREF1 Eight bank cyclic refresh, continuous VDD x9/x18 692 540 540 419 mA current address/data, command bus remains in refresh x36 670 545 545 430 for all banks VEXT 45 30 30 25 Disturbed IREF2 Single bank refresh, sequential bank access, VDD x9/x18 286 265 260 194 mA refresh current half address transitions once every tRC, x36 295 265 260 215 continuous data VEXT 10 10 10 10 Operating burst IDD2W BL=2, cyclic bank access, half of address bits VDD X9/x18 1078 872 872 716 mA write current change every clock cycle, continuous data, X36 1105 891 891 731 measurement is taken during continuous WRITE VEXT 40 35 35 30 Operating burst IDD4W BL=4, cyclic bank access, half of address bits VDD x9/x18 784 645 645 538 mA write current change every two clocks, continuous data, x36 832 681 681 565 measurement is taken during continuous WRITE VEXT 25 20 20 20 Operating burst IDD8W BL=8, cyclic bank access, half of address bits VDD x9/x18 625 520 520 442 mA write current change every four clocks, continuous data, x36 706 579 579 487 measurement is taken during continuous WRITE VEXT 25 20 20 20 Operating burst IDD2R BL=2, cyclic bank access, half of address bits VDD x9/x18 949 735 735 566 mA read current change every clock cycle, measurement is taken x36 999 779 779 601 during continuous READ VEXT 40 35 35 30 Operating burst IDD4R BL=4, cyclic bank access, half of address bits VDD x9/x18 659 503 503 400 mA read current change every two clocks, measurement is taken x36 685 535 535 424 during continuous READ VEXT 25 20 20 20 Operating burst IDD8R BL=8, cyclic bank access, half of address bits VDD x9/x18 497 389 389 308 mA read current change every four clocks, measurement is taken x36 567 441 441 349 during continuous READ VEXT 25 20 20 20 |
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