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UPD48576209F1 Arkusz danych(PDF) 26 Page - Renesas Technology Corp |
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UPD48576209F1 Arkusz danych(HTML) 26 Page - Renesas Technology Corp |
26 / 54 page µµµµPD48576209F1, µµµµPD48576218F1, µµµµPD48576236F1 R10DS0256EJ0101 Rev. 1.01 Page 26 of 53 Jan. 15, 2016 2.11 Read Operation (READ) Read accesses are initiated with a READ command, as shown in Figure 2-12. Row and bank addresses are provided with the READ command. During READ bursts, the memory device drives the read data edge-aligned with the QK signal. After a programmable READ latency, data is available at the outputs. The data valid signal indicates that valid data will be present in the next half clock cycle. The skew between QK and the crossing point of CK is specified as tCKQK. tQKQ0 is the skew between QK0 and the last valid data edge considered the data generated at the DQ0–DQ17 in x36 and DQ0–DQ8 in x18 data signals. tQKQ1 is the skew between QK1 and the last valid data edge considered the data generated at the DQ18–DQ35 in x36 and DQ9–DQ17 in x18 data signals. tQKQx is derived at each QKx clock edge and is not cumulative over time. After completion of a burst, assuming no other commands have been initiated, DQ will go High-Z. Back-to-back READ commands are possible, producing a continuous flow of output data. Minimum READ data valid window can be expressed as MIN.(tQKH, tQKL) – 2 x MAX.(tQKQx) Any READ burst may be followed by a subsequent WRITE command. Figure 2-16. READ followed by WRITE, BL=2, RL=4, WL=5, Configuration 1 and Figure 2-17. READ followed by WRITE, BL=4, RL=4, WL=5, Configuration 1 illustrate the timing requirements for a READ followed by a WRITE. Figure 2-12. READ Command Remark A : Address BA: Bank address CK# CK WE # REF# CS# ADDRESS BANK ADDRESS Don't care A BA |
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