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HT46R0042 Arkusz danych(PDF) 11 Page - Holtek Semiconductor Inc |
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HT46R0042 Arkusz danych(HTML) 11 Page - Holtek Semiconductor Inc |
11 / 83 page Rev. 1.00 10 ��to�e� ��� �01� Rev. 1.00 11 ��to�e� ��� �01� HT46R0042 Cost-Effective A/D 8-Bit OTP MCU HT46R0042 Cost-Effective A/D 8-Bit OTP MCU System Architecture Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributed totheinternalsystemarchitecture.Therangeofdevicetakeadvantageoftheusualfeaturesfound withinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance. Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstruction executionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withthe exceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyalloperations oftheinstructionset.Itcarriesoutarithmeticoperations,logicoperations,rotation,increment, decrement,branchdecisions,etc.Theinternaldatapathissimplifiedbymovingdatathroughthe AccumulatorandtheALU.CertaininternalregistersareimplementedintheDataMemoryand canbedirectlyorindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalong withadditionalarchitecturalfeaturesensurethataminimumofexternalcomponentsisrequiredto provideafunctionalI/OandA/Dsystemwithmaximumreliabilityandflexibility. Clocking and Pipelining Themainsystemclock,derivedfromHIRCoscillatorissubdividedintofourinternallygenerated non-overlappingclocks,T1~T4.TheProgramCounterisincrementedatthebeginningoftheT1 clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthe decodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle. Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncycles,the pipeliningstructureofthemicrocontrollerensuresthatinstructionsareeffectivelyexecutedinone instructioncycle.TheexceptiontothisareinstructionswherethecontentsoftheProgramCounter arechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemore instructioncycletoexecute. T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 Fe tc h IN ST ( PC ) Ex ec ut e IN ST ( PC -1 ) Fe tc h IN ST ( PC +1 ) Ex ec ut e IN ST ( PC ) Fe tc h IN ST ( PC +2 ) Ex ec ut e IN ST ( PC +1 ) PC PC +1 PC +2 S yst em C lo ck OS C2 ( RC on ly ) PC System Clocking and Pipelining Forinstructionsinvolvingbranches,suchasjumporcallinstructions,twoinstructioncyclesare requiredtocompleteinstructionexecution.Anextracycleisrequiredastheprogramtakesone cycletofirstlyobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethe branch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintiming sensitiveapplications. Fe tc h In st . 1E xe cu te I ns t . 1 Fe tc h In st . 2 Fl us h Pi pel in e 1 2 3 4 5 6 DE LA Y: MO V A, [1 2H ] CA LL D EL AY CP L [ 12H ] : : NO P Ex ec ut e In st . 2 Fe tc h In st . 3 Fe tc h In st . 6 Ex ec ut e In s t. 6 Fe tc h In st . 7 Instruction Fetching |
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