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HT56RB688 Arkusz danych(PDF) 94 Page - Holtek Semiconductor Inc |
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HT56RB688 Arkusz danych(HTML) 94 Page - Holtek Semiconductor Inc |
94 / 164 page External Interrupt For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bits, EEI0 and EEI1, must first be set. Additionally the correct interrupt edge type must be selected using the MISC0 register to enable the external interrupt function and to choose the trigger edge type. An actual external interrupt will take place when the external interrupt request flag, EIF0 or EIF1, is set, a situation that will occur when a transition, whose type is chosen by the edge select bit, appears on the INT0 or INT1 pin. The external interrupt pins are pin-shared with the I/O pins PA0 and PA1 and can only be configured as external interrupt pins if their corresponding external interrupt enable bit in the INTC0 or INTC1 register has been set. The pin must also be setup as an input by setting the corresponding PAC.0 and PAC.1 bits in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 0CH or 10H, will take place. When the interrupt is serviced, the external interrupt request flags, EIF0 or EIF1, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on this pin will remain valid even if the pin is used as an external interrupt input. The MISC0 register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising, falling or both rising and falling edge types can be chosen to trigger an external interrupt. Note that the MISC0 register can also be used to disable the external interrupt function. The external interrupt pins are connected to an internal filter to reduce the possibility of unwanted external interrupts due to adverse noise or spikes on the external interrupt input signal. As this internal filter circuit will consume a limited amount of power, the software control bits named INT0FLT and INT1FLT respectively in the RCFLT register are provided to switch off the filter function, an option which may be beneficial in power sensitive applications, but in which the integrity of the input signal is high. MISC0 Register Bit 76543210 Name CRDCKS1 CRDCKS0 SMF SMCEN INT1S1 INT1S0 INT0S1 INT0S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 00000000 Bit 7~6 CRDCKS1~CRDCKS0: Smart Card interface clock source divided ratio selection Described in the table below Bit 5 SMF: Smart Card clock output CCLK frequency fCCLK selection Described in the table below Bit 4 SMCEN: Smart Card interface clock control 0: fCRD is disabled 1: fCRD is enabled This bit is used to control the Smart Card interface clock source. If this bit is cleared to disable the clock, the relevant registers in the Smart Card interface module can not be accessed but will keep the original contents. When the Smart Card interface clock is disabled, it has no effect on the Card insertion or removal detections. Rev. 1.10 94 April 15, 2013 HT56RB688 TinyPowerTM A/D type Smart Card OTP MCU with LCD, DAC, ISO 7816 and USB Interfaces F i l t e r O n / O f f C o n t r o l I N T n F L T I N T 1 F i l t e r I N T 0 F i l t e r E x t e r n a l I N T . 0 E x t e r n a l I N T . 1 M C U |
Podobny numer części - HT56RB688_13 |
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Podobny opis - HT56RB688_13 |
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