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HT82K95EE Arkusz danych(PDF) 5 Page - Holtek Semiconductor Inc |
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HT82K95EE Arkusz danych(HTML) 5 Page - Holtek Semiconductor Inc |
5 / 43 page A.C. Characteristics Ta=25 °C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions fSYS System Clock (Crystal OSC) 5V ¾ 6 ¾ 12 MHz fTIMER Timer I/P Frequency (TMR) 5V ¾ 0 ¾ 12 MHz tWDTOSC Watchdog Oscillator 5V ¾ 15 31 70 ms tWDT1 Watchdog Time-out Period (WDT OSC) 5V Without WDT prescaler 4 8 16 ms tWDT2 Watchdog Time-out Period (System Clock) ¾ Without WDT prescaler ¾ 1024 ¾ tSYS tRES External Reset Low Pulse Width ¾¾ 1 ¾¾ ms tSST System Start-up Timer Period ¾ Wake-up from HALT ¾ 1024 ¾ tSYS Power-up, Watchdog Time-out from normal ¾ 1024 ¾ tWDTOSC tINT Interrupt Pulse Width ¾¾ 1 ¾¾ ms EEPROM A.C. Characteristics Ta=25 °C Symbol Parameter Remark Standard Mode* VCC=5V ±10% Unit Min. Max. Min. Max. fSK Clock Frequency ¾¾ 100 ¾ 400 kHz tHIGH Clock High Time ¾ 4000 ¾ 600 ¾ ns tLOW Clock Low Time ¾ 4700 ¾ 1200 ¾ ns tr SDA and SCL Rise Time Note ¾ 1000 ¾ 300 ns tf SDA and SCL Fall Time Note ¾ 300 ¾ 300 ns tHD:STA START Condition Hold Time After this period the first clock pulse is generated 4000 ¾ 600 ¾ ns tSU:STA START Condition Setup Time Only relevant for repeated START condition 4000 ¾ 600 ¾ ns tHD:DAT Data Input Hold Time ¾ 0 ¾ 0 ¾ ns tSU:DAT Data Input Setup Time ¾ 200 ¾ 100 ¾ ns tSU:STO STOP Condition Setup Time ¾ 4000 ¾ 600 ¾ ns tAA Output Valid from Clock ¾¾ 3500 ¾ 900 ns tBUF Bus Free Time Time in which the bus must be free before a new trans- mission can start 4700 ¾ 1200 ¾ ns tSP Input Filter Time Constant (SDA and SCL Pins) Noise suppression time ¾ 100 ¾ 50 ns tWR Write Cycle Time ¾¾ 5 ¾ 5ms Note: These parameters are periodically sampled but not 100% tested * The standard mode means VCC=2.2V to 5.5V For relative timing, refer to timing diagrams HT82K95EE/HT82K95AE Rev. 1.50 5 April 13, 2012 |
Podobny numer części - HT82K95EE_12 |
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Podobny opis - HT82K95EE_12 |
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