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ST16C2552IJ44 Arkusz danych(PDF) 11 Page - Exar Corporation |
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ST16C2552IJ44 Arkusz danych(HTML) 11 Page - Exar Corporation |
11 / 28 page 3-145 ST16C2552 MCR BIT-2: Not used except in local loop-back mode. MCR BIT-3: 0=force OP2* output to high. 1=force OP2* output to low. MCR BIT-4: 0=normal operating mode. 1=enable local loop-back mode (diagnostics). The transmitter output (TX) is set high (Mark condition), the receiver input (RX) , CTS*, DSR*, CD*, and RI* are disabled. Internally the transmitter output is con- nected to the receiver input and DTR*, RTS*, OP1* and OP2* are connected to modem control inputs. In this mode , the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational, but the interrupts sources are now the lower four bits of the Modem Control Register instead of the four Modem Control inputs. The inter- rupts are still controlled by the IER . MCR BIT 5-7: Not used. Are set to zero permanently. LINE STATUS REGISTER (LSR) This register provides the status of data transfer to CPU. LSR BIT-0: 0=no data in receive holding register or FIFO. 1=data has been received and saved in the receive holding register or FIFO. LSR BIT-1: 0=no overrun error (normal). 1=overrun error, next character arrived before receive holding register was emptied or if FIFOs are enabled, an overrun error will occur only after the FIFO is full and the next character has been completely received in the shift register. Note that character in the shift register is overwritten, but it is not transferred to the FIFO. LSR BIT-2: 0=no parity error (normal). 1=parity error, received data does not have correct parity information. In the FIFO mode this error is associated with the character at the top of the FIFO. LSR BIT-3: 0=no framing error (normal). 1=framing error received, received data did not have a valid stop bit. In the FIFO mode this error is associated with the character at the top of the FIFO. LSR BIT-4: 0=no break condition (normal). 1=receiver received a break signal (RX was low for one character time frame). In FIFO mode, only one zero character is loaded into the FIFO. LSR BIT-5: 0=transmit holding register is full. ST16C2552 will not accept any data for transmission. 1=transmit holding register (or FIFO ) is empty. CPU can load the next character. LSR BIT-6: 0=transmitter holding and shift registers are full. 1=transmitter holding and shift registers are empty. In FIFO mode this bit is set to one whenever the trans- mitter FIFO and transmit shift register are empty. LSR BIT-7: 0=Normal. 1=At least one parity error, framing error or break indication in the FIFO. This bit is cleared when LSR is read. MODEM STATUS REGISTER (MSR) This register provides the current state of the control lines from the modem or peripheral to the CPU. Four bits of this register are used to indicate the changed information. These bits are set to “1” whenever a control input from the MODEM changes state. They are set to “0” whenever the CPU reads this register. |
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