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STK14C88-3RF45I Arkusz danych(PDF) 10 Page - List of Unclassifed Manufacturers |
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10 / 13 page STK14C88-3 November 2003 10 Document Control # ML0015 rev 0.3 To operate in this mode the HSB pin should be con- nected together to the HSB pins from the other STK14C88-3s. An external pull-up resistor to + 3.3V is required since HSB acts as an open drain pull down. The V CAP pins from the other STK14C88-3 parts can be tied together and share a single capac- itor. The capacitor size must be scaled by the num- ber of devices connected to it. When any one of the STK14C88-3s detects a power loss and asserts HSB, the common HSB pin will cause all parts to request a STORE cycle (a STORE will take place in those STK14C88-3s that have been written since the last nonvolatile cycle). During any STORE operation, regardless of how it was initiated, the STK14C88-3 will continue to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of the STORE operation the STK14C88-3 will remain disabled until the HSB pin returns high. If HSB is not used, it should be left unconnected. HARDWARE PROTECT The STK14C88-3 offers hardware protection against inadvertent STORE operation and SRAM WRITEs dur- ing low-voltage conditions. When V CAP < VSWITCH, all externally initiated STORE operations and SRAM WRITE s will be inhibited. LOW AVERAGE ACTIVE POWER The STK14C88-3 draws significantly less current when it is cycled at times longer than 55ns. Figure 3 shows the relationship between I CC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial tem- perature range, V CC = 3.6V, 100% duty cycle on chip enable). Figure 4 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14C88-3 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the Vcc level; and 7) I/O loading. Figure 3: Icc (max) Reads Figure 4: Icc (max) Writes 0 10 20 30 40 50 50 100 150 200 Cycle Time (ns) TTL CMOS 0 10 20 30 40 50 50 100 150 200 Cycle Time (ns) TTL CMOS |
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