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RT5509 Arkusz danych(PDF) 22 Page - Richtek Technology Corporation

Numer części RT5509
Szczegółowy opis  Speaker Amplifier with Speaker Protection
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Producent  RICHTEK [Richtek Technology Corporation]
Strona internetowa  http://www.richtek.com
Logo RICHTEK - Richtek Technology Corporation

RT5509 Arkusz danych(HTML) 22 Page - Richtek Technology Corporation

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RT5509
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation
www.richtek.com
DS5509-00
August
2017
22
PWDN/SUSPD/Off/Fault/Mute mode. A register control
bit can be configured to set if the pilot is also turned off
in Silence mode. If yes, then the pilot should be turn off
after
signal
power
below
threshold
for
SilenceResetTime. This bit also defines if the DC
resistance is monitored or not in Silence mode.
Except for Fault mode, the pilot always turned on or
turned off at zero cross level. In worst case the pilot
turn-off latency will be 11.6ms.
Signal Detector
The signal activity is detected when the input signal
level is above a user defined threshold. The detection
window can be specified to be 5ms/10ms/20ms.
Another long time constant: SilenceRestTime is used to
ensure the silence happen and set the ALC to its initial
gain.
Parameters :
sThresAct : silence or active threshold (0 to
90dBFS,
6dB step)
SilenceResetTime : the time to reset ALC gain to initial
value (0 to 15 seconds)
Peak Detector
The peak detector monitors the peak of the signal
magnitude and the estimated excursion. The algorithm
is describe as following equation, with attack time can
be specified as 0ms/1ms/2ms/4ms and release time
can be specified by (1-RT) represented in 16-
bit 2’s
complement format.
xPeak(n) = (1-AT) xPeak(n-1)+AT
x(n)
xPeak(n) = (1-RT) xPeak(n-1)

for
x(n) >xPeak(n-1)
x(n)
xPeak(n-1)
Automatic Level Control (ALC)
The core of ALC gain control is depicted in Figure 15.
The gain is checked and adjusted every ALC_period,
which is specified by UpDoubleTime and DnHalfTime
registers. These two register bit fields has physical
meaning which mapped to approximately ±6dB per
second. They can be specified from 1/16 to 15.9375
seconds with resolution of 1/16s.
The internal logic implements ALC_period by a counter
expired every 16 * UpDoubleTime or 16 * DnHalfTime
when the gain is going up/dn respectively. Depend on
the clock base of I2S, the nominal of ±6dB per second
for double/half the gain is actually approximately by :
44.1k : 20*log10((4097/4096)^(48000/16)) = 6.36dB;
20*log10((4095/4096)^(48000/16)) =
6.36dB
48k : 20*log10((4097/4096)^(44100/16)) = 5.84dB;
20*log10((4095/4096)^(44100/16)) =
5.84dB
The Parameters for ALC Control :
sThresALC[7:0] : Threshold of signal, specified by 0 to
1. 1 corresponds to the maximum allowable signal
specified by clipper module.
xThresALC[7:0] : Threshold of excursion, specified by 0
to 1. 1 corresponds to the maximum allowable
excursion.
sThresALC and xThresALC are 8-bit unsigned number
representing the value 1/128 to 1, 0x80 is normalized
to 1.
UpDoubleTime[7:0]
:
gain
double
time
=
UpDoubleTime /16 (seconds)
DnHalfTime[7:0] : gain half time = DnHalfTime /16
(seconds)
InitUpDoubleTime[7:0] : gain double time used for
signal just detected from silence mode.
UpDoubleTime, DnHalfTime, InitUpDoubleTime and
InitDnHalfTime are unsigned 8-bit number representing
the value 1/16 to 15.9375, 0x10 is normalized to 1.
ALCInitGain[2:0] : ALC initial gain when signal is
detected from silence mode. 0 to 21dB, 3dB step.
ALCMaxGain[2:0] : ALC maximum allowable gain. 0 to
21dB, 3dB step.


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