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RT9107B Arkusz danych(PDF) 8 Page - Richtek Technology Corporation |
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RT9107B Arkusz danych(HTML) 8 Page - Richtek Technology Corporation |
8 / 42 page RT9107B 8 DS9107B-00 November 2016 www.richtek.com © Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit Repeated Start Condition Setup Time tSU, STA 0.6 -- -- s Stop Condition Time tSU, STD 0.6 -- -- s Data Hold Time tHD, DAT (OUT) 225 -- -- ns Input Data Hold Time tHD, DAT (IN) 0 -- 900 ns Data Setup Time tSU, DAT 100 -- -- ns Clock Low Period tLOW 1.3 -- -- s Clock High Period tHIGH 0.6 -- -- s Clock Data Fall Time tF 20 -- 300 ns Clock Data Rise Time tR 20 -- 300 ns Spike Suppression Time tSP -- -- 50 ns Slave mode I2S Interface Electrical Characteristics Parameter Symbol Test Conditions Min Typ Max Unit High-level Input Voltage VIH 2 -- -- V Low-level Input Voltage VIL -- -- 0.8 V Frequency fSCLKIN 1.024 -- 12.288 MHz Setup Time, LRCK to SCLK Rising Edge tsu1 10 -- -- ns Hold Time, LRCK from SCLK Rising Edge th1 10 -- -- ns Setup Time, SDIN to SCLK Rising Edge tsu2 10 -- -- ns Hold Time, SDIN from SCLK Rising Edge th2 10 -- -- ns Rise/Fall Time for SCLK/LRCLK tr -- -- 8 ns Rise/Fall Time for SCLK/LRCLK tf -- -- 8 ns LRCK SDIN /SDO SCLK tr tf th2 tsu2 tsu1 th1 Figure 1. Timing Diagram of Slave Mode I2S Interface |
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