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AD5241BRU100-REEL7 Arkusz danych(PDF) 10 Page - Analog Devices |
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AD5241BRU100-REEL7 Arkusz danych(HTML) 10 Page - Analog Devices |
10 / 16 page REV. B AD5241/AD5242 –10– DRWB (DEC) ( )Output State 255 10021 Full-Scale (RWB – 1 LSB + RW) 128 5060 Midscale 199 1 LSB 060Zero-Scale (Wiper Contact Resistance) Note that in the zero-scale condition, a finite wiper resistance of 60 Ω is present. Care should be taken to limit the current flow between W and B in this state to a maximum current of no more than ±20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. Similar to the mechanical potentiometer, the resistance of the RDAC between Wiper W and Terminal A also produces a digi- tally controlled resistance, RWA. When these terminals are used, the B Terminal can be opened or tied to the Wiper Terminal. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is: RD D RR WA AB W () =× + 256 256 – (2) For RAB = 10 k Ω, and the B Terminal can be either open circuit or tied to W. The following output resistance RWA will be set for the following RDAC latch codes. DRWA (DEC) ( ) Output State 255 99 Full-Scale 128 5060 Midscale 1 10021 1 LSB 0 10060 Zero-Scale The typical distribution of the nominal resistance RAB from channel to channel matches within ±1% for AD5242. Device- to-device matching is process lot dependent and it is possible to have ±30% variation. Since the resistance element is processed in thin film technology, the change in RAB with temperature has no more than a 30 ppm/ °C temperature coefficient. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates output voltages at wiper-to-B and wiper-to-A to be proportional to the input volt- age at A-to-B. Unlike the polarity of VDD – VSS, which must be positive, voltage across A–B, W–A, and W–B can be at either polarity provided that VSS is powered by a negative supply. If ignoring the effect of the wiper resistance for approximation, connecting the A Terminal to 5 V and the B Terminal to ground produces an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across Terminal AB divided by the 256 positions of the potentiometer divider. Since AD5241/AD5242 can be sup- plied by dual supplies, the general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminals A and B is: VD D V D V WA B () =+ − 256 256 256 (3) which can be simplified to VD D VV WAB B () =+ 256 (4) where D is the decimal equivalent of the binary code between 0 to 255 that is loaded in the 8-bit RDAC register. For more accurate calculation including the effects of wiper resistance, VW can be found as: VD RD R V RD R V W WB AB A WA AB B ()= () + () (5) where RWB(D) and RWA(D) can be obtained from Equations 1 and 2. Operation of the digital potentiometer in the Divider Mode results in a more accurate operation over temperature. Unlike the Rheostat Mode, the output voltage is dependent on the ratio of the internal resistors RWA and RWB, and not the absolute values; therefore, the temperature drift reduces to 5 ppm/ °C. DIGITAL INTERFACE 2-Wire Serial Bus The AD5241/AD5242 are controlled via an I 2C compatible serial bus. The RDACs are connected to this bus as slave devices. Referring to Figures 2 and 3, the first byte of AD5241/AD5242 is a Slave Address Byte. It has a 7-bit slave address and an R/ W Bit. The 5 MSBs are 01011 and the following two bits are determined by the state of the AD0 and AD1 Pins of the device. AD0 and AD1 allow users to use up to four of these devices on one bus. The 2-wire I 2C serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (Figure 2). The following byte is the Slave Address Byte, Frame 1, which consists of the 7-bit slave address followed by an R/ W Bit (this bit deter- mines whether data will be read from or written to the slave device). The slave whose address corresponds to the transmitted address will respond by pulling the SDA line low during the ninth clock pulse (this is termed the Acknowledge Bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/ W Bit is high, the master will read from the slave device. If the R/ W Bit is low, the master will write to the slave device. 2. A Write operation contains an extra Instruction Byte more than the Read operation. This Instruction Byte, Frame 2, in Write Mode follows the Slave Address Byte. The MSB of the Instruction Byte labeled A/B is the RDAC subaddress select. A “low” selects RDAC1 and a “high” selects RDAC2 for the dual-channel AD5242. Set A/B to low for AD5241. The second MSB, RS, is the midscale reset. A logic high of this bit moves the wiper of a selected RDAC to the center tap where RWA = RWB. The third MSB, SD, is a shutdown bit. A logic high on SD causes the RDAC open circuit at Terminal A while shorting the wiper to Terminal B. This operation yields almost a 0 Ω in Rheostat Mode or 0 V in Potentiometer Mode. This SD Bit serves the same function as the SHDN |
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