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ST7LITE1 Arkusz danych(PDF) 33 Page - STMicroelectronics |
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ST7LITE1 Arkusz danych(HTML) 33 Page - STMicroelectronics |
33 / 131 page ST7LITE1 33/131 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 7.6.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Reset Value: 0000 0xx0 (0xh) Bit 7:5 = Reserved, must be kept cleared. Bit 4 = WDGRF Watchdog reset flag This bit indicates that the last Reset was generat- ed by the Watchdog peripheral. It is set by hard- ware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table. Bit 3 = LOCKED PLL Locked Flag This bit is set and cleared by hardware. It is set au- tomatically when the PLL reaches its operating fre- quency. 0: PLL not locked 1: PLL locked Bit 2 = LVDRF LVD reset flag This bit indicates that the last Reset was generat- ed by the LVD block. It is set by hardware (LVD re- set) and cleared by software (by reading). When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined. Bit 1 = AVDF Voltage Detector flag This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is gen- erated when the AVDF bit is set. Refer to Figure 18 and to Section 7.6.2.1 for additional details. 0: VDD over AVD threshold 1: VDD under AVD threshold Bit 0 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag is set. The pending interrupt information is automati- cally cleared when software enters the AVD inter- rupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled Application notes The LVDRF flag is not cleared when another RE- SET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the origi- nal failure. In this case, a watchdog reset can be detected by software while an external reset can not. 70 00 0 WDG RF LOCKED LVDRF AVDF AVDIE RESET Sources LVDRF WDGRF External RESET pin 0 0 Watchdog 0 1 LVD 1 X 1 |
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