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AD7879 Arkusz danych(PDF) 22 Page - Analog Devices

Numer części AD7879
Szczegółowy opis  Low Voltage Controller for Touch Screens
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD7879 Arkusz danych(HTML) 22 Page - Analog Devices

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AD7879/AD7889
Data Sheet
Rev. D | Page 22 of 40
DETAILED REGISTER DESCRIPTIONS
All addresses and default values are expressed in hexadecimal.
Table 12. Control Register 1
Address
Bit Name
Data Bit
Description
Default Value
0x01
Disable PENIRQ
15
Pen interrupt enable.
0x0000
0 = PENIRQ is enabled.
1 = PENIRQ is disabled and INT is enabled.
CHNL ADD[2:0]
[14:12]
ADC channel address for manual conversion (ADC mode = 01).
111 = X+ input (Y position).
110 = Y+ input (X position).
101 = X+ (Z1) input for touch-pressure calculation.
100 = Y− (Z2) input (used for touch-pressure measurement).
011 = AUX input.1
010 = VBAT input.1
001 = temperature measurement.
000 = not applicable.
ADC MODE[1:0]
[11:10]
ADC mode.
00 = no conversion.
01 = single conversion.2
10 = conversion sequence (slave mode).2
11 = conversion sequence (master mode).
ACQ[1:0]
[9:8]
ADC acquisition time.
00 = 4 clock periods (2 µs).
01 = 8 clock periods (4 µs).
10 = 16 clock periods (8 µs).
11 = 32 clock periods (16 µs).
Note that the acquisition time does not apply to the temperature sensor
channels; the temperature channel has a constant settling time of 16 µs.
TMR[7:0]
[7:0]
Conversion interval timer.
Starts at 550 µs (00000001) and continues to 9.440 ms (11111111) in steps of
35 µs (see Table 18).
Note that, in slave mode, the conversion interval timer starts to count as soon
as the conversion sequence is finished; in master mode, it starts to count again
only if the screen remains touched. If the screen is released, the timer stops
counting and, on the next screen touch, a conversion starts immediately.
1 If GPIO is enabled in Control Register 2 (Bit 13), AUX and VBAT are both ignored. If AUX and VBAT are both selected in Control Register 3 and GPIO is disabled, AUX is
ignored and VBAT is measured.
2 Note that these bits are cleared to 00 at the end of the conversion sequence if the conversion interval timer bits in Control Register 1 (Address 0x01) Bits[7:0] = 0x00 at
the end of the conversion sequence.


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