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AD7729 Arkusz danych(PDF) 5 Page - Analog Devices

Numer części AD7729
Szczegółowy opis  Dual Sigma-Delta ADC with Auxiliary DAC
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD7729 Arkusz danych(HTML) 5 Page - Analog Devices

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AD7729
–4–
REV. 0
TIMING CHARACTERISTICS
Limit at
Parameter
TA = –40 C to +105 C
Units
Description
AUXILIARY FUNCTIONS
Clock Signals
See Figure 2.
t1
76
ns min
MCLK Period
t2
30.4
ns min
MCLK Width Low
t3
30.4
ns min
MCLK Width High
t4
t1
ns min
ASCLK Period. See Figures 4 and 6.
t5
0.4
× t
1
ns min
ASCLK Width Low
t6
0.4
× t
1
ns min
ASCLK Width High
t10
20
ns min
ASDI/ASDIFS Setup Before ASCLK Low
t11
10
ns min
ASDI/ASDIFS Hold After ASCLK Low
t12
15
ns max
ASDOFS Delay from ASCLK High
t13
0
ns min
ASDOFS Hold After ASCLK High
t14
0
ns min
ASDO Hold After ASCLK High
t15
15
ns max
ASDO Delay from ASCLK High
t16
10
ns min
ASDIFS Low to ASDI LSB Read by ASPORT
t17
t4 + 15
ns min
Interval Between Consecutive ASDIFS Pulses
Receive Section
Clock Signals
See Figures 5 and 7.
t7
t1
ns min
BSCLK Period
t8
0.4
× t
1
ns min
BSCLK Width Low
t9
0.4
× t
1
ns min
BSCLK Width High
t18
20
ns min
BSDI/BSDIFS Setup Before BSCLK Low
t19
10
ns min
BSDI/BSDIFS HoldAfter BSCLK Low
t20
15
ns max
BSDOFS Delay from BSCLK High
t21
0
ns min
BSDOFS Hold After BSCLK High
t22
0
ns min
BSDO Hold After BSCLK High
t23
15
ns max
BSDO Delay from BSCLK High
t24
10
ns min
BSDIFS Low to ASDI LSB Read by BSPORT
t25
t7 + 15
ns min
Interval Between Consecutive BSDIFS Pulses
ASCLK = MCLK/(2
× ASCLKRATE). ASCLKRATE can have a value from 0 . . . 1023. When ASCLKRATE = 0, ASCLK = 13 MHz.
BSCLK = MCLK/(2
× BSCLKRATE). BSCLKRATE can have a value from 0 . . . 1023. When BSCLKRATE = 0, BSCLK = 13 MHz.
Specifications subject to change without notice.
(AVDD1 = AVDD2 = +3 V
10%; DVDD1 = DVDD2 = +3 V
10%; AGND = DGND = 0 V;
TA = TMIN to TMAX, unless otherwise noted)
Table II. Receive Section Signal Ranges
Baseband Section
Signal Range
VREFCAP
1.3 V
± 5%
VREFOUT
1.3 V
± 10%
ADC
ADC Signal Range
2 VREFCAP
VBIAS
Differential Input
VREFCAP/2 to (AVDD1 – VREFCAP/2)
Single-Ended Input
VREFCAP to (AVDD1 – VREFCAP)
Signal Range
Differential
VBIAS
± V
REFCAP/2
Single-Ended
VBIAS
± V
REFCAP
Table III. Auxiliary Section Signal Ranges
AUXDAC
Signal Range
Output Code
Code 000
2/32
× V
REFCAP
Code 3FF
2 VREFCAP


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