AD7856

–9–

REV. A

ON-CHIP REGISTERS

The AD7856 powers up with a set of default conditions. The only writing that is required is to select the channel configuration.

Without performing any other write operations the AD7856 still retains the flexibility for performing a full power-down, and a full

self-calibration.

Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali-

bration, and software conversion start can be selected by further writing to the part.

The AD7856 contains a Control Register, ADC Output Data Register, Status Register, Test Register and ten Calibration

Registers. The control register is write only, the ADC output data register and the status register are read only, and the test and

calibration registers are both read/write registers. The Test Register is used for testing the part and should not be written to.

Addressing the On-Chip Registers

Writing

A write operation to the AD7856 consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine which register

is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are written that the

data is latched into the addressed registers. Table I shows the decoding of the address bits while Figure 4 shows the overall write

register hierarchy.

Table I. Write Register Addressing

ADDR1

ADDR0

Comment

0

0

This combination does not address any register so the subsequent 14 data bits are ignored.

0

1

This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the

test register.

1

0

This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are

written to the selected calibration register.

1

1

This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written

to the control register.

Reading

To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These

bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address

bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be

from the ADC output data register.

Once the read selection bits are set in the Control Register, all subsequent read operations that follow will be from the selected regis-

ter until the read selection bits are changed in the Control Register.

Table II. Read Register Addressing

RDSLT1

RDSLT0

Comment

0

0

All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-

up default setting. There will always be two leading zeros when reading from the ADC Output Data

Register.

0

1

All successive read operations will be from TEST REGISTER.

1

0

All successive read operations will be from CALIBRATION REGISTERS.

1

1

All successive read operations will be from STATUS REGISTER.

01

10

11

00

01

10

11

ADDR1, ADDR0

DECODE

TEST

REGISTER

CONTROL

REGISTER

GAIN(1)

OFFSET(1)

DAC(8)

GAIN(1)

OFFSET(1)

OFFSET(1)

GAIN(1)

CALIBRATION

REGISTERS

CALSLT1, CALSLT0

DECODE

Figure 4. Write Register Hierarchy/Address Decoding

01

10

11

00

01

10

11

TEST

REGISTER

STATUS

REGISTER

GAIN(1)

OFFSET(1)

DAC(8)

GAIN(1)

OFFSET(1)

OFFSET(1)

GAIN(1)

CALIBRATION

REGISTERS

00

ADC OUTPUT

DATA REGISTER

RDSLT1, RDSLT0

DECODE

CALSLT1, CALSLT0

DECODE

Figure 5. Read Register Hierarchy/Address Decoding