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AD7894AR-10 Arkusz danych(PDF) 8 Page - Analog Devices |
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AD7894AR-10 Arkusz danych(HTML) 8 Page - Analog Devices |
8 / 13 page AD7894 –7– REV. 0 Track/Hold Section The track/hold amplifier on the analog input of the AD7894 allows the ADC to accurately convert an input sine wave of full- scale amplitude to 14-bit accuracy. The input bandwidth of the track/hold is greater than the Nyquist rate of the ADC, even when the ADC is operated at its maximum throughput rate of 160 kHz (i.e., the track/hold can handle input frequencies in excess of 100 kHz). The track/hold amplifier acquires an input signal to 14-bit accu- racy in less than 0.35 µs. The operation of the track/hold is essentially transparent to the user. With the high sampling operating mode the track/hold amplifier goes from its tracking mode to its hold mode at the start of conversion (i.e., the falling edge of CONVST). The aperture time for the track/hold (i.e., the delay time between the external CONVST signal and the track/hold actually going into hold) is typically 15 ns. At the end of conversion (on the falling edge of BUSY) the part re- turns to its tracking mode. The acquisition time of the track/ hold amplifier begins at this point. For the auto shutdown mode, the rising edge of CONVST wakes up the part and the track and hold amplifier goes from its tracking mode to its hold mode 5 µs after the rising edge of CONVST (provided that the CONVST high time is less than 5 µs). Once again the part re- turns to its tracking mode at the end of conversion when the BUSY signal goes low. Reference Input The reference input to the AD7894 is buffered on-chip with a maximum reference input current of 1 µA. The part is specified with a +2.5 V reference input voltage. Errors in the reference source will result in gain errors in the AD7894’s transfer func- tion and will add to the specified full-scale errors on the part. Suitable reference sources for the AD7894 include the AD780 and AD680 precision +2.5 V references. Timing and Control Section Figure 3 shows the timing and control sequence required to obtain optimum performance from the AD7894. In the se- quence shown, conversion is initiated on the falling edge of CONVST and new data from this conversion is available in the output register of the AD7894 5 µs later. Once the read opera- tion has taken place, a further 250 ns should be allowed before the next falling edge of CONVST to optimize the settling of the track/hold amplifier before the next conversion is initiated. With the serial clock frequency at its maximum of 16 MHz, the achievable throughput rate for the part is 5 µs (conversion time) plus 1.0 µs (read time) plus 250 ns (quiet time). This results in a minimum throughput time of 6.25 µs (equivalent to a throughput rate of 160 kHz). A serial clock of less than 16 MHz can be used, but this will in turn mean that the throughput time will increase. The read operation consists of 16 serial clock pulses to the output shift register of the AD7894. After 16 serial clock pulses the shift register is reset and the SDATA line is three-stated. If there are more serial clock pulses after the 16th clock, the shift register will be moved on past its reset state. However, the shift register will be reset again on the falling edge of the CONVST signal to ensure that the part returns to a known state every conversion cycle. As a result, a read operation from the output register should not straddle across the falling edge of CONVST as the output shift register will be reset in the middle of the read operation and the data read back into the microprocessor will appear invalid. OPERATING MODES Mode 1 Operation (High Sampling Performance) The timing diagram in Figure 3 is for optimum performance in operating Mode 1 where the falling edge of CONVST starts conversion and puts the Track/Hold amplifier into its hold mode. This falling edge of CONVST also causes the BUSY signal to go high to indicate that a conversion is taking place. The BUSY signal goes low when the conversion is complete, which is 5 µs max after the falling edge of CONVST and new data from this conversion is available in the output register of the AD7894. A read operation accesses this data. This read operation consists of 16 clock cycles and the length of this read operation will depend on the serial clock frequency. For the fastest throughput rate (with a serial clock of 16 MHz) the read operation will take 1.0 µs. The read operation must be com- plete at least 250 ns before the falling edge of the next CONVST and this gives a total time of 6.25 µs for the full throughput time (equivalent to 160 kHz). This mode of operation should be used for high sampling applications. 250ns MIN t1 = 40ns MIN tCONVERT = 5 s BUSY SCLK CONVST CONVERSION IS INITIATED; TRACK/HOLD GOES INTO HOLD CONVERSION ENDS 5 s LATER SERIAL READ OPERATION READ OPERATION SHOULD END 250ns PRIOR TO NEXT FALLING EDGE OF CONVST OUTPUT SERIAL SHIFT REGISTER IS RESET Figure 3. Mode 1 Timing Operation Diagram for High Sampling Performance |
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