AD7895

–4–

REV. 0

PIN FUNCTION DESCRIPTION

Pin

Pin

No.

Mnemonic

Description

1

REF IN

Voltage Reference Input. An external reference source should be connected to this pin to provide the refer-

ence voltage for the AD7895’s conversion process. The REF IN input is buffered on chip. The nominal ref-

erence voltage for correct operation of the AD7895 is +2.5 V.

Analog Input Channel. The analog input range is

±10 V (AD7895-10), ±2.5 V (AD7895-3) and 0 V to

+2.5 V (AD7895-2).

3

GND

Analog Ground. Ground reference for track/hold, comparator, digital circuitry and DAC.

4

SCLK

Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7895.

A new serial data bit is clocked out on the falling edge of this serial clock. Data is guaranteed valid for 10 ns

after this falling edge so that data can be accepted on the falling edge when a fast serial clock is used. The

serial clock input should be taken low at the end of the serial data transmission.

5

SDATA

Serial Data Output. Serial data from the AD7895 is provided at this output. The serial data is clocked out

by the falling edge of SCLK, but the data can also be read on the falling edge of SCLK. This is possible

because data bit N is valid for a specified time after the falling edge of SCLK (data hold time) (see Figure 4).

Sixteen bits of serial data are provided with four leading zeros followed by the 12 bits of conversion data.

On the sixteenth falling edge of SCLK, the SDATA line is held for the data hold time and then is disabled

(three-stated). Output data coding is 2s complement for the AD7895-10, AD7895-3 and straight binary for

the AD7895-2.

6

BUSY

The BUSY pin is used to indicate when the part is doing a conversion. The BUSY pin will go high on the

falling edge of CONVST and will return low when the conversion is complete.

7

CONVST

Convert Start. Edge-triggered logic input. On the falling edge of this input, the track/hold goes into its hold

mode, and conversion is initiated. If CONVST is low at the end of conversion, the part goes into power-

down mode. In this case, the rising edge of CONVST “wakes up” the part.

Positive supply voltage, +5 V

± 5%.

PIN CONFIGURATION

DIP and SOIC

1

2

3

4

8

7

6

5

TOP VIEW

(Not to Scale)

AD7895

REF IN

SDATA

BUSY

CONVST

GND

SCLK