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TSL1401CS Arkusz danych(PDF) 4 Page - List of Unclassifed Manufacturers |
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4 / 14 page TSL1401CS 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS036A - AUGUST 2003 4 r r Copyright E 2003, TAOS Inc. The LUMENOLOGY r Company www.taosinc.com Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25°C, λp = 640 nm, tint = 5 ms, RL = 330 Ω, Ee = 11 µW/cm2 (unless otherwise noted) (see Note 3 and Note 4) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vout Analog output voltage (white, average over 128 pixels) 1.6 2 2.4 V Vdrk Analog output voltage (dark, average over 128 pixels) Ee = 0 0 0.1 0.2 V PRNU Pixel response nonuniformity See Note 5 ±4% ±10% Nonlinearity of analog output voltage See Note 6 ±0.4% FS Output noise voltage See Note 7 1 mVrms Re Responsivity See Note 8 25 35 44 V/ (µJ/cm2) V Analog output saturation voltage VDD = 5 V, RL = 330 Ω 4.5 4.8 V Vsat Analog output saturation voltage VDD = 3 V, RL = 330 Ω 2.5 2.8 V SE Saturation exposure VDD = 5 V, See Note 9 136 nJ/cm2 SE Saturation exposure VDD = 3 V, See Note 9 78 nJ/cm2 DSNU Dark signal nonuniformity All pixels, Ee = 0 See Note 10 0.02 0.05 V IL Image lag See Note 11 0.5% I Supply current VDD = 5 V, Ee = 0 2.8 4.5 mA IDD Supply current VDD = 3 V, Ee = 0 2.6 4.5 mA VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V IIH High-level input current VI = VDD 1 µA IIL Low-level input current VI = 0 1 µA Ci Input capacitance 5 pF NOTES: 3. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm. 4. All measurements made with a 0.1 µF capacitor connected between VDD and ground. 5. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU. 6. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white). 7. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period. 8. Re(min) = [Vout(min) - Vdrk(max)] ÷ (Ee × tint) 9. SE(min) = [Vsat(min) - Vdrk(min)] × 〈Ee × tint) ÷ [Vout(max) - Vdrk(min)] 10. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination. 11. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after a pixel is exposed to a white condition followed by a dark condition: IL + V out (IL) * V drk V out (white) * V drk 100 Timing Requirements (see Figure 1 and Figure 2) MIN NOM MAX UNIT tsu(SI) Setup time, serial input (see Note 12) 20 ns th(SI) Hold time, serial input (see Note 11 and Note 13) 0 ns tw Pulse duration, clock high or low 50 ns tr, tf Input transition (rise and fall) time 0 500 ns NOTES: 12. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns. 13. SI must go low before the rising edge of the next clock pulse. |
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