ATWILC3000 datasheet(29/40 Pages) ATMEL

Numer części	ATWILC3000

Szczegółowy opis	Single Chip IEEE 802.11 b/g/n Link Controller withIntegrated Bluetooth 4.0

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Producent	ATMEL [ATMEL Corporation]

Strona internetowa	http://www.atmel.com

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ATWILC3000 Single Chip IEEE 802.11 b/g/n Link Controller with

Integrated Bluetooth 4.0 [DATASHEET]

Atmel-42390D-ATWILC3000-MUT-SmartConnect-Datasheet_05/2016

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input clock is selectable between 104MHz, 52MHz, 26MHz, and 13MHz. The clock divider value is

programmable as 13 integer bits and three fractional bits (with 8.0 being the smallest recommended value for

normal operation). This results in the maximum supported baud rate of 10MHz / 8.0 = 13MBd. The 802.11

UART input clock is selectable between 10MHz, 5MHz, 2.5MHz, and 1.25MHz. The clock divider value is

programmable as 13 integer bits and three fractional bits (with 8.0 being the smallest recommended value for

normal operation). This results in the maximum supported baud rate of 10MHz / 8.0 = 1.25MBd.

The UART can be configured for seven or eight bit operation, with or without parity, with four different parity

types (odd, even, mark, or space), and with one or two stop bits. It also has RX and TX FIFOs, which ensure

reliable high speed reception and low software overhead transmission. FIFO size is 4x8 for both RX and TX

direction. The UART also has status registers showing the number of received characters available in the FIFO

and various error conditions, as well the ability to generate interrupts based on these status bits.

An example of UART receiving or transmitting a single packet is shown in Figure 9-7. This example shows 7-bit

data (0x45), odd parity, and two stop bits.

For more specific instructions, refer to ATWILC3000 Programming Guide.

Figure 9-7.

Example of UART RX or TX Packet

9.7

PCM Interface

ATWILC3000 provides a PCM/IOM interface for Bluetooth audio. This interface is compatible with industry

standard PCM and IOM2 compliant devices, such as audio codecs, line interfaces, TDM switches, and others.

The PCM audio interface supports both master and slave modes, full duplex operation, mono, and stereo. The

interface operates at 8kHz frame rate and supports bit rates up to 512 bits/frame (4.096Mbps). The PCM

interface pins are mapped as shown in Table 9-11.

Table 9-11.

ATWILC3000 PCM Interface Pin Mapping

Pin #

PCM Function

36

CLK: Bi-directional clock input/output

37

SYNC: Bi-directional Frame sync (mono) or Left-Right Channel identifier (stereo)

38

D_IN: Serial data input

39

D_OUT: Serial data output

9.8

GPIOs

18 General Purpose Input/Output (GPIO) pins, labeled GPIO 0-8 and 13-21, are available to allow for

application specific functions. Each GPIO pin can be programmed as an input (the value of the pin can be read

by the host or internal processor) or as an output (the output values can be programmed by the host or internal

processor), where the default mode after power-up is input. GPIOs 7 and 8 are only available when the host

does not use the SDIO interface, which shares two of its pins with these GPIOs. Therefore, for SDIO-based

applications, 16 GPIOs (0-6 and 13-21) are available. For more specific instructions refer to ATWILC3000

Programming Guide.

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