AD574A

REV. B

–9–

Figure 7 shows a complete timing diagram for the AD574A con-

vert start operation. R/C should be low before both CE and CS

are asserted; if R/C is high, a read operation will momentarily

occur, possibly resulting in system bus contention. Either CE or

CS

may be used to initiate a conversion; however, use of CE is

recommended since it includes one less propagation delay than

CS

and is the faster input. In Figure 7, CE is used to initiate the

conversion.

Figure 7. Convert Start Timing

Once a conversion is started and the STS line goes high, convert

start commands will be ignored until the conversion cycle is

complete. The output data buffers cannot be enabled during

conversion.

Figure 8 shows the timing for data read operations. During data

read operations, access time is measured from the point where

CE and R/C both are high (assuming CS is already low). If CS

is used to enable the device, access time is extended by 100 ns.

Figure 8. Read Cycle Timing

In the 8-bit bus interface mode (12/8 input wired to DIGITAL

prior to CE going high and must remain stable during the entire

output buffers may result.

Table III. Read Timing—Full Control Mode

Symbol

Parameter

Min Typ

Max

Units

1

Access Time (from CE)

200

ns

Data Valid After CE Low

25

ns

2

Output Float Delay

100

ns

CS

to CE Setup

150

ns

R/C to CE Setup

0

ns

150

ns

CS

Valid After CE Low

50

ns

R/C High After CE Low

0

ns

50

ns

NOTES

required for an output to cross 0.4 V or 2.4 V.

loaded with the circuit of Figure 10.

a. High-Z to Logic 1

b. High-Z to Logic 0

Figure 9. Load Circuit for Access Time Test

a. Logic 1 to High-Z

b. Logic 0 to High-Z

Figure 10. Load Circuit for Output Float Delay Test

“STAND-ALONE” OPERATION

The AD574A can be used in a “stand-alone” mode, which is

useful in systems with dedicated input ports available and thus

not requiring full bus interface capability.

low, and conversion is controlled by R/C. The three-state buff-

ers are enabled when R/C is high and a conversion starts when

R/C goes low. This allows two possible control signals—a high

pulse or a low pulse. Operation with a low pulse is shown in

Figure 11. In this case, the outputs are forced into the high

impedance state in response to the falling edge of R/C and return

Figure 11. Low Pulse for R/C—Outputs Enabled After

Conversion