Zakładka z wyszukiwarką danych komponentów |
|
AD7701ARS Arkusz danych(PDF) 11 Page - Analog Devices |
|
AD7701ARS Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 21 page REV. E –10– AD7701 The output settling of the AD7701 in response to a step input change is shown in Figure 12. The Gaussian response has fast settling with no overshoot, and the worst-case settling time to ± 0.0007% (± 0.5 LSB) is 125 ms with a 4.096 MHz master clock frequency. 100 80 60 40 20 0 040 80 120 160 TIME – ms Figure 12. AD7701 Step Response USING THE AD7701 SYSTEM DESIGN CONSIDERATIONS The AD7701 operates differently from successive approxima- tion ADCs or other integrating ADCs. Since it samples the signal continuously, like a tracking ADC, there is no need for a start convert command. The 16-bit output register is updated at a 4 kHz rate, and the output can be read at any time, either synchronously or asynchronously. CLOCKING The AD7701 requires a master clock input, which may be an external TTL/CMOS compatible clock signal applied to the CLKIN pin (CLKOUT not used). Alternatively, a crystal of the correct frequency can be connected between CLKIN and CLKOUT, when the clock circuit will function as a crystal controlled oscillator. The input sampling frequency, output data rate, filter character- istics, and calibration time are all directly related to the master clock frequency, fCLKIN, by the ratios given in the specification table. Therefore, the first step in system design with the AD7701 is to select a master clock frequency suitable for the bandwidth and output data rate required by the application. ANALOG INPUT RANGES The AD7701 performs conversion relative to an externally supplied reference voltage that allows easy interfacing to ratiometric systems. In addition, either unipolar or bipolar input voltage ranges may be selected using the BP/ UP input. With BP/ UP tied low, the input range is unipolar and the span is 0 to +VREF. With BP/UP tied high, the input range is bipolar and the span is ±VREF. In the Bipolar mode, both positive and negative full scale are directly determined by VREF. This offers superior tracking of positive and negative full scale and better midscale (bipolar zero) stability than bipolar schemes that simply scale and offset the input range. The digital output coding for the unipolar range is unipolar binary; for the bipolar range it is offset binary. Bit weights for the Unipolar and Bipolar modes are shown in Table I. The input voltages and output codes for unipolar and bipolar ranges, using the recommended +2.5 V reference, are shown in Table II. Table I. Bit Weight Table (2.5 V Reference Voltage) Unipolar Mode Bipolar Mode µV LSBs % FS ppm FS LSBs % FS ppm FS 10 0.26 0.0004 4 0.13 0.0002 2 19 0.5 0.0008 8 0.26 0.0004 4 38 1.00 0.0015 15 0.5 0.0008 8 76 2.00 0.0031 31 1.00 0.0015 15 153 4.00 0.0061 61 2.00 0.0031 31 Table II. Output Coding Unipolar Mode Bipolar Mode Input Relative to Input Relative to FS and AGND Input (V) FS and AGND Input (V) Output Data 1111 1111 1111 1111 +VREF – 1.5 LSB +2.499943 +VREF – 1.5 LSB +2.499886 1111 1111 1111 1110 +VREF – 2.5 LSB +2.499905 +VREF – 2.5 LSB +2.499810 1111 1111 1111 1101 +VREF – 3.5 LSB +2.499867 +VREF – 3.5 LSB +2.499733 1111 1111 1111 1100 1000 0000 0000 0001 +VREF/2 + 0.5 LSB +1.250019 AGND + 0.5 LSB +0.000038 1000 0000 0000 0000 +VREF/2 – 0.5 LSB +1.249981 AGND – 0.5 LSB –0.000038 0111 1111 1111 1111 +VREF/2 – 1.5 LSB +1.249943 AGND – 1.5 LSB –0.000114 0111 1111 1111 1110 0000 0000 0000 0011 AGND + 2.5 LSB +0.000095 –VREF + 2.5 LSB –2.499810 0000 0000 0000 0010 AGND + 1.5 LSB +0.000057 –VREF + 1.5 LSB –2.499886 0000 0000 0000 0001 AGND + 0.5 LSB +0.000019 –VREF + 0.5 LSB –2.499962 0000 0000 0000 0000 NOTES 1. VREF = 2.5 V 2. AGND = 0 V 3. Unipolar Mode, 1 LSB = 2.5 V/655536 = 0.000038 V 4. Bipolar Mode, 1 LSB = 5 V/65536 = 0.000076 V 5. Inputs are voltages at code transitions. |
Podobny numer części - AD7701ARS |
|
Podobny opis - AD7701ARS |
|
|
Link URL |
Polityka prywatności |
ALLDATASHEET.PL |
Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |