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AD5590BBCZ Arkusz danych(PDF) 10 Page - Analog Devices |
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AD5590BBCZ Arkusz danych(HTML) 10 Page - Analog Devices |
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10 / 45 page  AD5590 Rev. A | Page 9 of 44 TIMING SPECIFICATIONS ADC Timing Characteristics ADCVDD = 2.7 V to 5.25 V, VDRIVE ≤ ADCVDD, VREFA = 2.5 V; All specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter1 Limit at TMIN, TMAX; ADCVDD = 5 V Unit Conditions/Comments fSCLK2 10 kHz min 20 MHz min tCONVERT 16 × tASCLK MHz max tQUIET 50 ns min t2 10 ns min ASYNC to ASCLK setup time t33 14 ns max Delay from ASYNC until ADOUT three-state disabled t3b4 20 ns min Data hold time t43 40 ns max Data access time after ASCLK falling edge t5 0.4 × tASCLK ns min ASCLK low pulse width t6 0.4 × tASCLK ns min ASCLK high pulse width t7 15 ns min ASCLK to ADOUT valid hold time t85 15/50 ns min/max ASCLK falling edge to ADOUT high impedance t9 20 ns min ADIN setup time prior to ASCLK falling edge t10 5 ns min ADIN Hold time prior to ASCLK falling edge t11 20 ns min 16th ASCLK falling edge to ASYNC high t12 1 µs max Power-up time from full power-down/autoshutdown/ autostandby modes 1 Guaranteed by design and characterization. Not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of ADCVDD) and timed from a voltage level of 1.6 V. 2 Maximum ASCLK frequency is 50 MHz at ADCVDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested. 3 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE. 4 t3b represents a worst-case figure for having ADD3 available on the ADOUT line, that is, if the ADC goes back into three-state at the end of a conversion and some other device takes control of the bus between conversions, the user needs to wait a maximum time of t3b before having ADD3 valid on the ADOUT line. If the ADOUT line is weakly driven to ADD3 between conversions, then the user typically needs to wait 17 ns at 3 V and 12 ns at 5 V after the ASYNC falling edge before seeing ADD3 valid on ADOUT. 5 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish time of the part and is independent of bus loading. ASCLK ADOUT ADIN ASYNC WRITE SEQ ADD3 ADD2 ADD1 ADD0 DONTC DONTC DONTC ADD2 ADD1 ADD0 DB11 DB10 DB2 DB1 DB0 B t2 t3b t3 1 2 3 4 5 6 13 14 15 16 t9 t10 t8 t4 t7 t6 t5 t11 tQUIET tCONVERT THREE- STATE THREE- STATE ADD3 FOUR IDENTIFICATION BITS Figure 2. ADC Timing Characteristics 200µA IOL 200µA IOH 1.6V TO OUTPUT PIN CL 25pF Figure 3. Load Circuit for ADC Digital Output Timing Specifications |
Podobny numer części - AD5590BBCZ |
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Podobny opis - AD5590BBCZ |
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