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AD7294 Arkusz danych(PDF) 10 Page - Analog Devices |
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AD7294 Arkusz danych(HTML) 10 Page - Analog Devices |
10 / 48 page Data Sheet AD7294 Rev. I | Page 9 of 47 TIMING CHARACTERISTICS I2C Serial Interface AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, VREF = 2.5 V internal or external; VDRIVE = 2.7 V to 5.5 V; VPP = AVDD to 59.4 V; DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating, therefore, DAC output span = 0 V to 5 V; TA = −40°C to +105°C, unless otherwise noted. Table 4. Parameter1 Limit at TMIN, TMAX Unit Description fSCL 400 kHz max SCL clock frequency t1 2.5 μs min SCL cycle time t2 0.6 μs min tHIGH, SCL high time t3 1.3 μs min tLOW, SCL low time t4 0.6 μs min tHD,STA, start/repeated start condition hold time t5 100 ns min tSU,DAT, data setup time t6 0.9 μs max tHD,DAT, data hold time 0 μs min tHD,DAT, data hold time t7 0.6 μs min tSU,STA, setup time for repeated start t8 0.6 μs min tSU,STO, stop condition setup time t9 1.3 μs min tBUF, bus free time between a stop and a start condition t10 300 ns max tR, rise time of SCL and SDA when receiving 0 ns min tR, rise time of SCL and SDA when receiving (CMOS compatible) t11 300 ns max tF, fall time of SDA when transmitting 0 ns min tF, fall time of SDA when receiving (CMOS compatible) 300 ns max tF, fall time of SCL and SDA when receiving 20 + 0.1Cb2 ns min tF, fall time of SCL and SDA when transmitting Cb 400 pF max Capacitive load for each bus line 1 See Figure 2. 2 Cb is the total capacitance in pF of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD. Timing and Circuit Diagrams START CONDITION REPEATED START CONDITION STOP CONDITION t9 t3 t1 t11 t4 t10 t4 t5 t7 t6 t8 t2 SDA SCL Figure 2. I2C-Compatible Serial Interface Timing Diagram CL 50pF TO OUTPUT PIN VOH (MIN) OR VOL (MAX) 200µA 200µA IOL IOH Figure 3. Load Circuit for Digital Output |
Podobny numer części - AD7294 |
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Podobny opis - AD7294 |
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