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AD9874EB Arkusz danych(PDF) 2 Page - Analog Devices |
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AD9874EB Arkusz danych(HTML) 2 Page - Analog Devices |
2 / 40 page REV. 0 –2– Parameter Temp Test Level Min Typ Max Unit SYSTEM DYNAMIC PERFORMANCE 2 SSB Noise Figure @ Min VGA Attenuation 3, 4 Full IV 8.1 9.5 dB @ Max VGA Attenuation 3, 4 Full IV 13 dB Dynamic Range with AGC Enabled 3, 4 Full IV 91 95 dB IF Input Clip Point @ Max VGA Attenuation 3 Full IV –20 –19 dBm @ Min VGA Attenuation 3 Full IV –32 –31 dBm Input Third Order Intercept (IIP3) Full IV –5 0 dBm Gain Variation over Temperature Full IV 0.7 2 dB LNA + MIXER Maximum RF and LO Frequency Range Full IV 300 500 MHz LNA Input Impedance 25 oCV 370//1.4 Ω//pF Mixer LO Input Resistance 25 oCV 1 k Ω LO SYNTHESIZER LO Input Frequency Full IV 7.75 300 MHz LO Input Amplitude Full IV 0.3 2.0 V p-p FREF (Reference) Frequency Full IV 0.1 25 MHz FREF Input Amplitude Full IV 0.3 3 V p-p Minimum Charge Pump Current @ 5 V5 Full VI 0.48 0.67 0.78 mA Maximum Charge Pump Current @ 5 V5 Full VI 3.87 5.3 6.2 mA Charge Pump Output Compliance 6 Full VI 0.4 VDDP – 0.4 V Synthesizer Resolution Full IV 6.25 kHz CLOCK SYNTHESIZER CLK Input Frequency Full IV 13 26 MHz CLK Input Amplitude Full IV 0.3 VDDC V p-p Minimum Charge Pump Output Current 5 Full VI 0.48 0.67 0.78 mA Maximum Charge Pump Output Current 5 Full VI 3.87 5.3 6.2 mA Charge Pump Output Compliance 6 Full VI 0.4 VDDQ – 0.4 V Synthesizer Resolution Full IV 2.2 kHz SIGMA-DELTA ADC Resolution Full IV 16 24 Bits Clock Frequency (fCLK) Full IV 13 26 MHz Center Frequency Full V fCLK/8 MHz Pass-Band Gain Variation Full IV 1.0 dB Alias Attenuation Full IV 80 dB GAIN CONTROL Programmable Gain Step Full V 16 dB AGC Gain Range (Continuous) Full V 12 dB OVERALL Analog Supply Voltage (VDDA, VDDF, VDDI) Full VI 2.7 3.0 3.6 V Digital Supply Voltage (VDDD, VDDC, VDDL) Full VI 2.7 3.0 3.6 V Interface Supply Voltage 7 (VDDH) Full VI 1.8 3.6 V Charge Pump Supply Voltage (VDDP, VDDQ) Full VI 2.7 5.0 5.5 V Total Current High Performance Setting 8 Full VI 20 26.5 mA Low Power Mode 8 Full VI 17 22 mA Standby Full VI 0.01 0.1 mA OPERATING TEMPERATURE RANGE –40 +85 °C NOTES 1 Standard operating mode: LNA/Mixer @ high bias setting, VGA @ Min ATTEN setting, synthesizers in normal (not fast acquire) mode, f CLK = 18 MHz, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins. 2 This includes 0.9 dB loss of matching network. 3 AGC with DVGA enabled. 4 Measured in 10 kHz bandwidth. 5 Programmable in 0.67 mA steps. 6 Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2). 7 VDDH must be less than VDDD + 0.5 V. 8 Clock VCO off, add additional 0.7 mA with VGA @ Max ATTEN setting. Specifications subject to change without notice. (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = 2.7 to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, fCLK = 18 MSPS, fIF = 109.65 MHz, fLO = 107.4 MHz, fREF = 16.8 MHz, unless otherwise noted.) 1 AD9874–SPECIFICATIONS |
Podobny numer części - AD9874EB |
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Podobny opis - AD9874EB |
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