Zakładka z wyszukiwarką danych komponentów |
|
AD9670EBZ Arkusz danych(PDF) 9 Page - Analog Devices |
|
AD9670EBZ Arkusz danych(HTML) 9 Page - Analog Devices |
9 / 48 page AD9674 Data Sheet Rev. A | Page 8 of 47 SWITCHING SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, full temperature range (0°C to 85°C), RF decimator bypassed, and digital HPF bypassed, unless otherwise noted. Table 3. Parameter1 Temperature Min Typ Max Unit CLOCK2 Clock Rate 40 MSPS (Mode I) Full 20.5 40 MHz 65 MSPS (Mode II) Full 20.5 65 MHz 80 MSPS (Mode III)3 Full 20.5 80 MHz 125 MSPS (Mode IV)4 Full 20.5 125 MHz Clock Pulse Width High (tEH) Full 3.75 ns Clock Pulse Width Low (tEL) Full 3.75 ns OUTPUT PARAMETERS2, 5 Propagation Delay (tPD) Full 10.8 − 1.5 × tDCO 10.8 10.8 + 1.5 × tDCO ns Rise Time (tR) (20% to 80%) Full 300 ps Fall Time (tF) (20% to 80%) Full 300 ps DCO± Period (tDCO)6 Full tSAMPLE/7 ns FCO± Propagation Delay (tFCO) Full 10.8 − 1.5 × tDCO 10.8 10.8 + 1.5 × tDCO ns DCO± Propagation Delay (tCPD)7 Full tFCO + (tSAMPLE/28) ns DCO± to Data Delay (tDATA)7 Full (tSAMPLE/28) − 300 tSAMPLE/28 (tSAMPLE/28) + 300 ps DCO± to FCO± Delay (tFRAME)7 Full (tSAMPLE/28) − 300 tSAMPLE/28 (tSAMPLE/28) + 300 ps Data to Data Skew (tDATA-MAX − tDATA-MIN) Full ±225 ±400 ps TX_TRIG± to CLK± Setup Time (tSETUP) 25°C 1 ns TX_TRIG± to CLK± Hold Time (tHOLD) 25°C 1 ns Wake-Up Time (Standby) 25°C 2 µs Wake-Up Time (Power-Down) 25°C 375 µs ADC Pipeline Latency Full 16 Clock cycles APERTURE Aperture Uncertainty (Jitter), tA 25°C <1 ps rms LO GENERATION MLO± Frequency 4LO Mode Full 4 40 MHz 8LO Mode Full 8 80 MHz 16LO Mode Full 16 160 MHz RESET± to MLO± Setup Time (tSETUP) Full 1 tMLO/2 ns RESET± to MLO± Hold Time (tHOLD) Full 1 tMLO/2 ns 1 For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, UnderstandingHigh SpeedADCTestingandEvaluation. 2 The clock can be adjusted via the SPI. 3 Mode III must have the RF decimator enabled, unless DVDD runs at 1.8 V and 12-bit mode is configured. 4 Mode IV must have the RF decimator enabled. 5 Measurements were made using the device soldered to FR-4 material. 6 tSAMPLE/7 is based on the number of bits (14) divided by 2 because the interface uses DDR sampling. 7 tSAMPLE/28 is based on the number of bits (14) multiplied by 2 because the delays are based on half duty cycles. |
Podobny numer części - AD9670EBZ |
|
Podobny opis - AD9670EBZ |
|
|
Link URL |
Polityka prywatności |
ALLDATASHEET.PL |
Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |