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SLG46108 Arkusz danych(PDF) 58 Page - Dialog Semiconductor |
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SLG46108 Arkusz danych(HTML) 58 Page - Dialog Semiconductor |
58 / 70 page 000-0046108-108 Page 57 of 69 SLG46108 14.0 Appendix A - SLG46108 Register Definition Register Bit Address Signal Function Register Bit Definition reg <4:0> Pin3 digital out source reg <9:5> Pin4 digital out source reg <14:10> Pin4 output enable reg <19:15> in0 of LUT2_0 (Clock Input of DFF0) reg <24:20> in1 of LUT2_0 (Data Input of DFF0) reg <29:25> in0 of LUT2_1 (Clock Input of DFF1) reg <34:30> in1 of LUT2_1 (Data Input of DFF1) reg <39:35> in0 of LUT2_2 reg <44:40> in1 of LUT2_2 reg <49:45> in0 of LUT2_3 reg <54:50> in1 of LUT2_3 reg <59:55> in0 of LUT3_0 (Clock Input of DFF2 with nReset/nSet) reg <64:60> in1 of LUT3_0 (Data input of DFF2 with nReset/nSet) reg <69:65> in2 of LUT3_0 (Resetb or Setb of DFF2 with nRe- set/nSet) reg <74:70> in0 of LUT3_1 (Clock Input of DFF3 with nReset/nSet) reg <79:75> in1 of LUT3_1 (Data input of DFF3 with nReset/nSet) reg <84:80> in2 of LUT3_1 (Resetb or Setb of DFF3 with nRe- set/nSet) reg <89:85> in0 of LUT3_2 reg <94:90> in1 of LUT3_2 reg <99:95> in2 of LUT3_2 reg <104:100> in0 of LUT3_3 reg <109:105> in1 of LUT3_3 reg <114:110> in2 of LUT3_3 reg <119:115> in0 of LUT3_4 (Input of pipe delay) reg <124:120> in1 of LUT3_4 (Resetb of pipe delay) reg <129:125> in2 of LUT3_4 (Clock of pipe delay) reg <134:130> in0 of LUT4_0 (Input for Delay2 ext. clock or Counter2 external Clock) reg <139:135> in1 of LUT4_0 (Input for delay2 or counter2 reset input) reg <144:140> in2 of LUT4_0 (Input for counter2 FSM keep signal) reg <149:145> in3 of LUT4_0 (Input for counter2 FSM up signal) reg <154:150> Input for delay0 or counter0 reset input reg <159:155> Input for delay1 or counter1 reset input reg <164:160> Input for Delay 0/1(Counter 0/1) external clock reg <169:165> Input for delay3 or counter3 reset input reg <174:170> Input for programmable delay (deglitch filter input) reg <179:175> Power down for osc. (higher priority) (high = power down). reg <184:180> Pin6 digital out source reg <189:185> Pin7 digital out source |
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