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SLG46127 Arkusz danych(PDF) 54 Page - Dialog Semiconductor |
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SLG46127 Arkusz danych(HTML) 54 Page - Dialog Semiconductor |
54 / 88 page 000-0046127-101 Page 53 of 87 SLG46127 12.3 CNT/DLY3 Register Settings Table 40. CNT/DLY3 Register Settings Signal Function Register Bit Address Register Definition Counter/Delay3 Mode Select reg <342> 0: Delay Mode 1: Counter Mode Counter/Delay3 Clock Source Select (external clock is only for counter mode) reg <345:343> 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock 111: Counter2 Overflow Counter3 Control Data/Delay3 Time Control reg <353:346> 1-255: (delay time = (counter control data +2) /freq) Delay3 Mode Select reg <355:354> 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges |
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