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SLG46200 Arkusz danych(PDF) 42 Page - Dialog Semiconductor |
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SLG46200 Arkusz danych(HTML) 42 Page - Dialog Semiconductor |
42 / 69 page 000-0046200-124 Page 37 of 64 SLG46200 16.0 Counters (CNT) There are three configurable 14-bit counters in the SLG46200. CNT2’s input can be sourced from the NVM, the ADC, or the S2P, while CNT0 and CNT1’s input can be sourced from the connection matrix. The clock can be sourced from either the internal RC Oscillator (with data divider for CNT1) or from another connection matrix output. The counters output their data to either the PWM or to the S2P. FSM functions include: count UP, count DOWN, KEEP, LOAD ONCE, and LOAD DATA (taken from either registers, ADC, or S2P). The three counters can also function as frequency dividers, FSM (CNT2), or PWM ramp (CNT1), while captured data is outputted to S2P. When in count DOWN mode, the count UP/DOWN, KEEP, and LOAD signals in CNT0 and CNT1 are tied to ground and the RC OSC should be forced ON for counter work. 16.1 Counter Functional Diagram 16.2 Counter Timing Each of the counters behave as a frequency divider, where the output clock (Div_clk_out) is result of the input clock (CLK_IN) being divided by the value of the Counter Control Data (CNTx_d<13:0> +1). For CNT0: div_clk_out0 = FCLK_IN / (reg<432:419> + 1) For CNT1: div_clk_out1 = FCLK_IN / (reg<446:433> + 1) For CNT2: div_clk_out2 = FCLK_IN / (reg<460:447> + 1) Note: For proper functionality of each Counter cell, each respective CNTx_d<13:0> must have a value of greater than ‘1’. Figure 22. Counter Functional Diagram Counter CNTx_cki_ext CNTx_out_sel CNTx_en CNTx_clk_is CNTx_d<13:0> OUT To Connection Matrix CLK4DLY |
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