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ADC32RF44 Arkusz danych(PDF) 10 Page - Texas Instruments

Numer części ADC32RF44
Szczegółowy opis  Dual-Channel, 14-Bit, 2.6-GSPS, Analog-to-Digital Converter
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
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ADC32RF44 Arkusz danych(HTML) 10 Page - Texas Instruments

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ADC32RF44
SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017
www.ti.com
Product Folder Links: ADC32RF44
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
(1)
Overall latency = latency + tPD.
(2)
Latency increases when the DDC modes are used; see Table 4.
(3)
Common-mode voltage for the SYSREF input is kept at 1.2 V.
7.8 Timing Requirements
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
MIN
NOM
MAX
UNIT
SAMPLE TIMING
Aperture delay
250
750
ps
Aperture delay matching between two channels on the same device
±15
ps
Aperture delay matching between two devices at the same
temperature and supply voltage
±150
ps
Aperture jitter, clock amplitude = 2 VPP
90
fS
Latency
(1) (2)
Data latency, ADC sample to
digital output
12-bit bypass mode, LMFS = 82820
461
Input
clock
cycles
14-bit bypass mode, LMFS = 8224
424
Input
clock
cycles
Fast overrange latency, ADC sample to FOVR indication on GPIO pins
70
tPD
Propagation delay time: logic gates and output buffer delay
(does not change with fS)
6
ns
SYSREF TIMING(3)
tSU_SYSREF SYSREF setup time: referenced to clock rising edge, 2.6 GSPS
140
70
ps
tH_SYSREF
SYSREF hold time: referenced to clock rising edge, 2.6 GSPS
50
20
ps
Valid transition window sampling period: tSU_SYSREF – tH_SYSREF, 2.6 GSPS
194
ps
JESD OUTPUT INTERFACE TIMING
UI
Unit interval: 12.5 Gbps
80
100
400
ps
Serial output data rate
2.5
10.0
12.5
Gbps
Rise, fall times: 1-pF, single-ended load capacitance to ground
60
ps
Total jitter: BER of 1E-15 and lane rate = 12.5 Gbps
25
%UI
Random jitter: BER of 1E-15 and lane rate = 12.5 Gbps
0.99
%UI, rms
Deterministic jitter: BER of 1E-15 and lane rate = 12.5 Gbps
9.1
%UI,
pk-pk


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