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ADC32RF44 Arkusz danych(PDF) 1 Page - Texas Instruments |
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ADC32RF44 Arkusz danych(HTML) 1 Page - Texas Instruments |
1 / 134 page ADC ADC ADC ADC ADC ADC INAP, INAM SYSREFP, SYSREFM CLKINP, CLKINM PLL 65 Buffer INBP, INBM 65 Buffer DB[1:0]P, DB[1:0]M DA[1:0]P, DA[1:0]M DA[3:2]P, DA[3:2]M DB[3:2]P, DB[3:2]M GPIO[4:1] ADC N N NCO CTRL SYNCBP, SYNCBM NCO FOVR FOVR NCO NCO NCO ADC Digital Block Interleave Correction Power Detection Digital Block Interleave Correction Power Detection Copyright © 2017, Texas Instruments Incorporated Clock Divider SPI and Control CM N N RESET SCLK SDATA SEN PDN SDO Product Folder Order Now Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADC32RF44 SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017 ADC32RF44 Dual-Channel, 14-Bit, 2.6-GSPS, Analog-to-Digital Converter 1 1 Features 1 • 14-Bit, Dual-Channel, 2.6-GSPS ADC • Noise Floor: –154.2 dBFS/Hz • RF Input Supports Up to 4.0 GHz • Aperture Jitter: 90 fS • Channel Isolation: 95 dB at fIN = 1.8 GHz • Spectral Performance (fIN = 900 MHz, –2 dBFS): – SNR: 61.2 dBFS – SFDR: 65-dBc HD2, HD3 – SFDR: 79-dBc Worst Spur • Spectral Performance (fIN = 1.85 GHz, –2 dBFS): – SNR: 58.3 dBFS – SFDR: 69-dBc HD2, HD3 – SFDR: 74-dBc Worst Spur • On-Chip Digital Down-Converters: – Up to 4 DDCs (Dual-Band Mode) – Up to 3 Independent NCOs per DDC • On-Chip Input Clamp for Overvoltage Protection • Programmable On-Chip Power Detectors with Alarm Pins for AGC Support • On-Chip Dither • On-Chip Input Termination • Input Full-Scale: 1.35 VPP • Support for Multi-Chip Synchronization • JESD204B Interface: – Subclass 1-Based Deterministic Latency – 4 Lanes Per Channel at 12.5 Gbps • Power Dissipation: 2.95 W/Ch at 2.6 GSPS • 72-Pin VQFN Package (10 mm × 10 mm) 2 Applications • Multi-Band, Multi-Mode 2G, 3G, 4G Cellular Receivers • Phased Array Radars • Electronic Warfare • Cable Infrastructure • Broadband Wireless • High-Speed Digitizers • Software-Defined Radios • Communications Test Equipment • Microwave and Millimeter Wave Receivers 3 Description The ADC32RF44 device is a 14-bit, 2.6-GSPS, dual- channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF44 delivers a noise spectral density of –154.2 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front- end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms. The ADC32RF44 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C). Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) ADC32RF44 VQFN (72) 10.00 mm × 10.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Block Diagram |
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