Zakładka z wyszukiwarką danych komponentów |
|
AD7878BQ Arkusz danych(PDF) 7 Page - Analog Devices |
|
AD7878BQ Arkusz danych(HTML) 7 Page - Analog Devices |
7 / 17 page AD7878 –6– REV. A INTERNAL FIFO MEMORY The internal FIFO memory of the AD7878 consists of eight memory locations. Each word in memory contains 13 bits of information—12 bits of data from the conversion result and one additional bit which contains information as to whether the 12- bit result is out of range or not. A block diagram of the AD7878 FIFO architecture is shown in Figure 3. Figure 3. Internal FIFO Architecture The conversion result is gathered in the successive approxima- tion register (SAR) during conversion. At the end of conversion this result is transferred to the FIFO memory. The FIFO ad- dress pointer always points to the top of memory, which is the uppermost location containing valid data. The pointer is incre- mented after each conversion. A read operation from the FIFO memory accesses data from the bottom of the FIFO, Location 0. On completion of the read operation, each data word moves down one location and the address pointer is decremented by one. Therefore, each conversion result from the SAR enters at the top of memory, propagates down with successive reads until it reaches Location 0 from where it can be accessed by a micro- processor read operation. The transfer of information from the SAR to the FIFO occurs in synchronization with the AD7878 input clock (CLK IN). The propagation of data words down the FIFO is also synchronous with this clock. As a result, a read operation to obtain data from the FIFO must also be synchronous with CLK IN to avoid Read/Write conflicts in the FIFO (i.e., reading from FIFO Loca- tion 0 while it is being updated). This requires that the micro- processor clock and the AD7878 CLK IN are derived from the same source. INTERNAL COMPARATOR TIMING The ADC clock, which is applied to CLK IN, controls the suc- cessive approximation A/D conversion process. This clock is internally divided by four to yield a bit trial cycle time of 500 ns min (CLK IN = 8 MHz clock). Each bit decision occurs 25 ns after the rising edge of this divided clock. The bit decision is latched by the rising edge of an internal comparator strobe sig- nal. There are 12-bit decisions, as in a normal successive ap- proximation routine, and one extra decision that checks if the input sample is out of range. In a normal successive approxima- tion A/D converter, reading data from the device during conver- sion can upset the conversion in progress. This is due to on-chip transients, generated by charging or discharging the databus, concurrent with a bit decision. The scheme outlined below and shown in Figure 4 describes how the AD7878 overcomes this problem. The internal comparator strobe on the AD7878 is gated with both DMRD and DMWR so that if a read or write operation occurs when a bit decision is about to be made, the bit decision point is deferred by one CLK IN cycle. In other words, if DMRD or DMWR goes low (with CS low) at any time during the CLK IN low time immediately prior to the comparator strobing edge (tLOW of Figure 4), the bit trial is suspended for a clock cycle. This makes sure that the bit decision is latched at a time when the AD7878 is not attempting to charge or discharge the data bus, thereby ensuring that no spurious transients occur internally near a bit decision point. The decision point slippage mechanism is shown in Figure 4 for the MSB decision. Normally, the MSB decision occurs 25 ns after the fourth rising CLK IN edge after CONVST goes high. However, in the timing diagram of Figure 4, CS and DMRD or DMWR are low in the time period t LOW prior to the MSB deci- sion point on the fourth rising edge. This causes the internal comparator strobe to be slipped to the fifth rising clock edge. The AD7878 will again check during a period tLOW prior to this fifth rising clock edge; and if the CS and DMRD or DMWR are still low, the bit decision point will be slipped a further clock cycle. The conversion time for the ADC normally consists of the 13- bit trials described above and one extra internal clock cycle during which data is written from the SAR to the FIFO. For an 8 MHz input clock this results in a conversion time of 7 µs. However, the software routine servicing the AD7878 has the potential to read 16 times from the device during conversion—8 reads from the FIFO and 8 reads from the status/control register. It also has the potential to write once to the status/control register. If these Figure 4. Operational Timing Diagram |
Podobny numer części - AD7878BQ |
|
Podobny opis - AD7878BQ |
|
|
Link URL |
Polityka prywatności |
ALLDATASHEET.PL |
Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |