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UC1845JQMLV Arkusz danych(PDF) 6 Page - Texas Instruments |
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UC1845JQMLV Arkusz danych(HTML) 6 Page - Texas Instruments |
6 / 3 page 6 High peak currents associated with capacitive loads ne- cessitate careful grounding techniques. Timing and by- pass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. Shutdown of the UC1842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset domi- nant so that the output will remain low until the next clock cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At this point the reference turns off, al- lowing the SCR to reset. UC1842/3/4/5 UC2842/3/4/5 OUTPUT SATURATION CHARACTERISTICS ERROR AMPLIFIER OPEN-LOOP FREQUENCY RESPONSE OPEN-LOOP LABORATORY FIXTURE SHUT DOWN TECHNIQUES |
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