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SN74AUP1G00DRLR Arkusz danych(PDF) 1 Page - Texas Instruments

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Numer części SN74AUP1G00DRLR
Szczegółowy opis  LOW-POWER SINGLE 2-INPUT POSITIVE-NAND GATE
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Producent  TI [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI - Texas Instruments

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SN74AUP1G00
LOW POWER SINGLE 2INPUT POSITIVENAND GATE
SCES604A – SEPTEMBER 2004 – REVISED APRIL 2005
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Available in the Texas Instruments
NanoStar
 and NanoFree Packages
D Low Static-Power Consumption;
ICC = 0.9-µA Max
D Low Dynamic-Power Consumption;
Cpd = 4 pF Typical at 3.3 V
D Low Input Capacitance; Ci = 1.5 pF Typical
D Low Noise − Overshoot and Undershoot
<10% of VCC
D Ioff Supports Partial-Power-Down Mode
Operation
D Input Hysteresis Allows Slow Input
Transition and Better Switching Noise
Immunity at the Input
(Vhys = 250 mV Typical at 3.3 V)
D Wide Operating VCC Range of 0.8 V to 3.6 V
D Optimized for 3.3-V Operation
D 3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
D tpd = 4.8 ns Max at 3.3 V
D Suitable for Point-to-Point Applications
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
D ESD Protection Exceeds ±5000-V With
Human-Body Model
DBV, DCK, OR DRL PACKAGE
(TOP VIEW)
1
2
3
5
4
A
B
GND
VCC
Y
3
2
1
4
5
GND
B
A
Y
VCC
YEP OR YZP PACKAGE
(BOTTOM VIEW)
description /ordering information
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see
Figures 1 and 2).
Figure 1. AUP−The Lowest-Power Family
AUP
LVC
AUP
AUP
LVC
Static-Power Consumption
(
µA)
Dynamic-Power Consumption
(pF)
† Single, dual, and triple gates.
3.3-V
Logic
3.3-V
Logic
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
05
10
15
20
25
30
35
40
45
Figure 2. Excellent Signal Integrity
Time − ns
AUP1G08 data at C
L = 15 pF.
Switching Characteristics
at 25 MHz†
Output
Input
This single 2-input positive-NAND gate performs the Boolean function Y = A
• B or Y = A + B in positive logic.
NanoStar
 and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
Copyright
 2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.


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