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ADF4154BCP Arkusz danych(PDF) 3 Page - Analog Devices |
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ADF4154BCP Arkusz danych(HTML) 3 Page - Analog Devices |
3 / 20 page ADF4154 Rev. 0 | Page 3 of 20 SPECIFICATIONS Table 1. AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. The operating temperature for the B version is −40°C to +80°C. Parameter B Version Unit Test Conditions/Comments RF CHARACTERISTICS (3 V) See Figure 18 for input circuit. RF Input Frequency (RFIN)1 0.5/4.0 GHz min/max −8 dBm/0 dBm min/max. For lower frequencies, ensure slew rate > 396 V/µs. 1.0/4.0 GHz min/max −10 dBm/0 dBm min/max. REFERENCE CHARACTERISTICS See Figure 17 for input circuit. REFIN Input Frequency1 10/250 MHz min/max For f < 10 MHz, use a dc-coupled, CMOS compatible square wave, slew rate > 21 V/µs. REFIN Input Sensitivity 0.7/AVDD V p-p min/max AC-coupled. 0 to AVDD V max CMOS compatible. REFIN Input Capacitance 10 pF max REFIN Input Current ±100 µA max PHASE DETECTOR Phase Detector Frequency2 32 MHz max CHARGE PUMP ICP Sink/Source Programmable. See Table 5. High Value 5 mA typ With RSET = 5.1 kΩ. Low Value 312.5 µA typ Absolute Accuracy 2.5 % typ With RSET = 5.1 kΩ. RSET Range 1.5/10 kΩ min/max ICP Three-State Leakage Current 1 nA typ Sink and source current. Matching 2 % typ 0.5 V < VCP < VP – 0.5. ICP vs. VCP 2 % typ 0.5 V < VCP < VP – 0.5. ICP vs. Temperature 2 % typ VCP = VP/2. LOGIC INPUTS VINH, Input High Voltage 1.4 V min VINL, Input Low Voltage 0.6 V max IINH/IINL, Input Current ±1 µA max CIN, Input Capacitance 10 pF max LOGIC OUTPUTS VOH, Output High Voltage 1.4 V min Open-drain 1 kΩ pull-up to 1.8 V. VOL, Output Low Voltage 0.4 V max IOL = 500 µA. POWER SUPPLIES AVDD 2.7/3.3 V min/V max DVDD, SDVDD AVDD VP AVDD/5.5 V min/V max IDD3 24 mA max 20 mA typical. Low Power Sleep Mode 1 µA typ NOISE CHARACTERISTICS Phase Noise Figure of Merit4 −213 dBc/Hz typ ADF4154 Phase Noise Floor5 −143 dBc/Hz typ @ 10 MHz PFD frequency. −139 dBc/Hz typ @ 26 MHz PFD frequency. Phase Noise Performance6 @ VCO output. 1750 MHz Output7 −102 dBc/Hz typ @ 1 kHz offset, 26 MHz PFD frequency. 1 Use a square wave for frequencies below fMIN. 2 Guaranteed by design. Sample tested to ensure compliance. 3 AC coupling ensures AVDD/2 bias. See for typical circuit. Figure 17 4 This figure can be used to calculate phase noise for any application. Use the formula –213 + 10log(fPFD) + 20logN to calculate in-band phase noise performance, as seen at the VCO output. The value given is the lowest noise mode. 5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N-divider value). The value given is the lowest noise mode. 6 The phase noise is measured with the EVAL-ADF4154EB1 evaluation board and the HP8562E spectrum analyzer. 7 fREFIN = 26 MHz; fPFD = 26 MHz; offset frequency = 1 kHz; RFOUT = 1750 MHz; loop B/W = 20 kHz; lowest noise mode. |
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