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CY7C1441KV33 Arkusz danych(PDF) 9 Page - Cypress Semiconductor |
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CY7C1441KV33 Arkusz danych(HTML) 9 Page - Cypress Semiconductor |
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9 / 32 page  CY7C1441KV33 CY7C1443KV33 CY7C1441KVE33 Document Number: 001-66677 Rev. *I Page 9 of 32 lines are tristated once a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BWX) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQS is written into the specified address location. Byte writes are allowed. All I/Os are tristated when a write is detected, even a byte write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tristated prior to the presentation of data to DQs. As a safety precaution, the data lines are tristated once a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 provide an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE selects a linear burst sequence. A HIGH on MODE selects an interleaved burst order. Leaving MODE unconnected causes the device to default to a interleaved burst sequence. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2,CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. On-Chip ECC CY7C1441KVE33 SRAMs include an on-chip ECC algorithm that detects and corrects all single-bit memory errors, including Soft Error Upset (SEU) events induced by cosmic rays, alpha particles etc. The resulting Soft Error Rate (SER) of these devices is anticipated to be <0.01 FITs/Mb a 4-order-of-magnitude improvement over comparable SRAMs with no On-Chip ECC, which typically have an SER of 200 FITs/Mb or more. To protect the internal data, ECC parity bits (invisible to the user) are used. The ECC algorithm does not correct multi-bit errors. However, Cypress SRAMs are designed in such a way that a single SER event has a very low probability of causing a multi-bit error across any data word. The extreme rarity of multi-bit errors results in a SER of <0.01 FITs/Mb. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 75 mA tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC –ns tZZI ZZ active to sleep current This parameter is sampled – 2tCYC ns tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 – ns |
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