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CY7C1618KV18 Arkusz danych(PDF) 15 Page - Cypress Semiconductor

Numer części CY7C1618KV18
Szczegółowy opis  144-Mbit DDR II SRAM Two-Word Burst Architecture
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Producent  CYPRESS [Cypress Semiconductor]
Strona internetowa  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1618KV18 Arkusz danych(HTML) 15 Page - Cypress Semiconductor

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Document Number: 001-44274 Rev. *N
Page 15 of 32
CY7C1618KV18/CY7C1620KV18
TAP Controller Block Diagram
0
0
1
2
.
.
29
30
31
Boundary Scan Register
Identification Register
0
1
2
.
.
.
.
108
0
1
2
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TCK
TMS
TAP Electrical Characteristics
Over the Operating Range
Parameter [13, 14, 15]
Description
Test Conditions
Min
Max
Unit
VOH1
Output high voltage
IOH =2.0 mA
1.4
V
VOH2
Output high voltage
IOH =100 A1.6
V
VOL1
Output low voltage
IOL = 2.0 mA
0.4
V
VOL2
Output low voltage
IOL = 100 A–
0.2
V
VIH
Input high voltage
0.65 × VDD VDD + 0.3
V
VIL
Input low voltage
–0.3
0.35 × VDD
V
IX
Input and output load current
GND
 VI  VDD
–5
5
A
Notes
13. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 21.
14. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > -1.5 V (Pulse width less than tCYC/2).
15. All voltage referenced to ground.


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