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CY7C1618KV18 Arkusz danych(PDF) 26 Page - Cypress Semiconductor

Numer części CY7C1618KV18
Szczegółowy opis  144-Mbit DDR II SRAM Two-Word Burst Architecture
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Producent  CYPRESS [Cypress Semiconductor]
Strona internetowa  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1618KV18 Arkusz danych(HTML) 26 Page - Cypress Semiconductor

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Document Number: 001-44274 Rev. *N
Page 26 of 32
CY7C1618KV18/CY7C1620KV18
Switching Waveforms
Read/Write/Deselect Sequence
Figure 6. Read/Write/Deselect Sequence [35, 36, 37]
Notes
35. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
36. Outputs are disabled (High Z) one clock cycle after a NOP.
37. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.


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