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CY7C1648KV18 Arkusz danych(PDF) 5 Page - Cypress Semiconductor

Numer części CY7C1648KV18
Szczegółowy opis  144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
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Producent  CYPRESS [Cypress Semiconductor]
Strona internetowa  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1648KV18 Arkusz danych(HTML) 5 Page - Cypress Semiconductor

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Document Number: 001-44061 Rev. *L
Page 5 of 29
CY7C1648KV18
CY7C1650KV18
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
Input Output-
Synchronous
Data input output signals. Inputs are sampled on the rising edge of K and K clocks during valid write
operations. These pins drive out the requested data when the read operation is active. Valid data is
driven out on the rising edge of both the K and K clocks during read operations. When read access is
deselected, Q[x:0] are automatically tristated.
CY7C1648KV18
 DQ[17:0]
CY7C1650KV18
 DQ[35:0]
LD
Input-
Synchronous
Synchronous load. Sampled on the rising edge of the K clock. This input is brought low when a bus
cycle sequence is defined. This definition includes address and read/write direction. All transactions
operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Synchronous
Byte write select (BWS) 0, 1, 2, and 3
 Active low. Sampled on the rising edge of the K and K clocks
during write operations. Used to select which byte is written into the device during the current portion of
the write operations. Bytes not written remain unaltered.
CY7C1648KV18
 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1650KV18
 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the byte write selects are sampled on the same edge as the data. Deselecting a BWS ignores the
corresponding byte of data and it is not written into the device.
A
Input-
Synchronous
Address inputs. Sampled on the rising edge of the K clock during active read and write operations.
These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 8 M × 18 (2 arrays each of 4 M × 18) for CY7C1648KV18, and 4 M × 36 (2 arrays each of
2 M × 36) for CY7C1650KV18.
R/W
Input-
Synchronous
Synchronous read or write input. When LD is low, this input designates the access type (read when
R/W is high, write when R/W is low) for loaded address. R/W must meet the setup and hold times around
edge of K.
QVLD
Valid output
indicator
Valid output indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
K
Input Clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
K
Input Clock Negative input clock input. K is used to capture synchronous data being presented to the device and
to drive out data through Q[x:0].
CQ
Echo Clock Synchronous echo clock outputs. This is a free-running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 22.
CQ
Echo Clock Synchronous echo clock outputs. This is a free-running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 22.
ZQ
Input
Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
DOFF
Input
PLL turn off
 Active low. Connecting this pin to ground turns off the PLL inside the device. The timing
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull-up through a 10 k
 or less pull-up resistor. The device behaves in DDR I
mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to
167 MHz with DDR I timing.
TDO
Output
Test data-out (TDO) pin for JTAG.
TCK
Input
Test clock (TCK) pin for JTAG.
TDI
Input
Test data-in (TDI) pin for JTAG.
TMS
Input
Test mode select (TMS) pin for JTAG.
NC
N/A
Not connected to the die. Can be tied to any voltage level.


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