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CS5233-3GDFR8 Arkusz danych(PDF) 8 Page - ON Semiconductor

Numer części CS5233-3GDFR8
Szczegółowy opis  500 mA and 1.5 A, 3.3 V Dual Input Linear Regulator with Auxiliary Control
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Producent  ONSEMI [ON Semiconductor]
Strona internetowa  http://www.onsemi.com
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CS5233-3GDFR8 Arkusz danych(HTML) 8 Page - ON Semiconductor

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CS5233−3
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8
respond. One of the consequences of providing this current
is an instantaneous voltage drop at VIN due to capacitor
ESR. The magnitude of the voltage change is again the
product of the current change and the capacitor ESR.
It is very important to consider the maximum current step
that can exist in the system. If the change in current is large
enough, it is possible that the instantaneous voltage drop on
VIN will exceed the VIN threshold hysteresis, and the IC will
enter a mode of operation resembling an oscillation. As the
part turns on, the output current IOUT will increase, reaching
current limit during initial charging. Increasing IOUT results
in a drop at VIN such that the shutdown threshold is reached.
The part will turn off, and the load current will decrease. As
IOUT decreases, VIN will rise and the part will turn on,
starting the cycle all over again. This oscillatory operation
is most likely at initial start−up when the output capacitance
is not charged, and in cases where the ramp−up of the VIN
supply is slow. It may also occur during the power transition
when the linear regulator turns on and the PFET turns off. A
20
ms delay exists between turn−on of the regulator and the
AuxDrv pin pulling the gate of the PFET high. This delay
prevents “chatter” during the power transitions.
If required, using a few capacitors in parallel to increase
the bulk charge storage and reduce the ESR should give
better performance than using a single input capacitor.
Short, straight connections between the power supply and
VIN lead along with careful layout of the PC board ground
plane will reduce parasitic inductance effects. Wide VIN and
VOUT traces will reduce resistive voltage drops.
Choosing the PFET Switch
The choice of the external PFET switch is based on two
main considerations. First, the PFET should have a very low
turn−on threshold. Choosing a switch transistor with
VGS(ON) ≈ 1.0 V will ensure the PFET will be fully enhanced
with only 3.3 V of gate drive voltage. Second, the switch
transistor should be chosen to have a low RDS(ON) to
minimize the voltage drop due to current flow in the switch.
The formula for calculating the maximum allowable
on−resistance is
RDS(ON)MAX +
VAUX(MIN) * VOUT(MIN)
1.5
IOUT(MAX)
VAUX(MIN) is the minimum value of the auxiliary supply
voltage, VOUT(MIN) is the minimum allowable output
voltage, IOUT(MAX) is the maximum output current and 1.5
is a “fudge factor” to account for increases in RDS(ON) due
to temperature.
Output Voltage Sensing
It is not possible to remotely sense the output voltage of
the C5233−3 since the feedback path to the error amplifier
is not externally available. It is important to minimize
voltage drops due to metal resistance of high current PC
board traces. Such voltage drops can occur in both the
supply traces and the return traces.
The following board layout practices will help to
minimize output voltage errors:
• Always place the linear regulator as close to both load
and output capacitors as possible.
• Always use the widest possible traces to connect the
linear regulator to the capacitor network and to the
load.
• Connect the load to ground through the widest possible
traces.
• Connect the IC ground to the load ground trace at the
point where it connects to the load.
Current Limit
The CS5233−3 has internal current limit protection.
Output current is limited to a typical value of 3.0 A for the
D2PAK using VIN and 800 mA using VSB, even under output
short circuit conditions. If the load current drain exceeds the
current limit value, the output voltage will be pulled down
and will result in an out of regulation condition.
Thermal Shutdown
The CS5233−3 has internal temperature monitoring
circuitry. The output is disabled if junction temperature of
the IC reaches 180
°C. Thermal hysteresis is typically 25°C
and allows the IC to recover from a thermal fault without the
need for an external reset signal. The monitoring circuitry is
located near the composite PNP−NPN output transistor,
since this transistor is responsible for most of the on−chip
power dissipation. The combination of current limit and
thermal shutdown will protect the IC from nearly any fault
condition.
Reverse Current Protection
During normal system operation, the auxiliary drive
circuitry will maintain voltage on the VOUT pin. IC
reliability and system efficiency are improved by limiting
the amount of reverse current that flows from VOUT to
ground and from VOUT to VIN. Current flows from VOUT to
ground through the feedback resistor divider that sets up the
output voltage, typically 400
mA. Current flow from VOUT
to VIN will be limited to leakage current after the IC shuts
down. On−chip RC time constants are such that the output
transistor should be turned off well before VIN drops below
the VOUT voltage.
Calculating Power Dissipation and
Heatsink Requirements
Most linear regulators operate under conditions that result
in high on−chip power dissipation. This results in high
junction temperatures. Since the IC has a thermal shutdown
feature, ensuring the regulator will operate correctly under
normal conditions is an important design consideration.
Some heatsinking will usually be required.
Thermal characteristics of an IC depend on four
parameters: ambient temperature (TA in °C), power
dissipation (PD in watts), thermal resistance from the die to


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