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AD5247EVAL Datasheet(Arkusz danych) 4 Page - Analog Devices

Numer części AD5247EVAL
Szczegółowy opis  128-Position I2C Compatible Digital Potentiometer
Pobierz  20 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD5247
Rev. 0 | Page 4 of 20
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
Table 2. VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C; unless otherwise noted
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
R-DNL
RWB, VA = No Connect
–1
±0.1
+1
LSB
Resistor Integral Nonlinearity2
R-INL
RWB, VA = No Connect
–2
±0.25
+2
LSB
Nominal Resistor Tolerance3
∆RAB
–20
+20
%
Resistance Temperature Coefficient
∆RAB/∆T
VA = VDD, Wiper = No Connect
45
ppm/°C
RWB
RWB
Code = 0x00
75
300
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Differential Nonlinearity4
DNL
–1
±0.1
+1
LSB
Integral Nonlinearity4
INL
–1
±0.2
+1
LSB
Voltage Divider Temperature Coefficient
∆VW/∆T
Code = 0x40
15
ppm/°C
Full-Scale Error (50 kΩ, 100 kΩ)
VWFSE
Code = 0x7F
–1
–1
0
LSB
Zero-Scale Error (50 kΩ, 100 kΩ)
VWZSE
Code = 0x00
0
+0.4
+1
LSB
Full-Scale Error (10 kΩ)
VWFSE
Code = 0x7F
–2
–0.5
0
LSB
Zero-Scale Error (10 kΩ)
VWZSE
Code = 0x00
0
+0.5
+1
LSB
RESISTOR TERMINALS
Voltage Range5
VA, W
GND
VDD
V
Capacitance6 A
CA
f = 1 MHz, Measured to GND,
Code = 0x40
45
pF
Capacitance6 W
CW
f = 1 MHz, Measured to GND,
Code = 0x40
60
pF
Common-Mode Leakage
ICM
VA = VDD/2
1
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
VDD = 5V
2.4
V
Input Logic Low
VIL
VDD = 5 V
0.8
V
Input Logic High
VIH
VDD = 3 V
2.1
V
Input Logic Low
VIL
VDD = 3 V
0.6
V
Input Current
IIL
VIN = 0 V or 5 V
±1
µA
Input Capacitance6
CIL
5
pF
POWER SUPPLIES
Power Supply Range
VDD RANGE
2.7
5.5
V
Supply Current
IDD
VIH = 5 V or VIL = 0 V
3
8
µA
Power Dissipation7
PDISS
VIH = 5 V or VIL = 0 V, VDD = 5 V
40
µW
Power Supply Sensitivity
PSSR
VDD = +5 V ± 10%, Code = Midscale
±0.01
±0.02
%/%
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB
BW
RAB = 10 kΩ/50 kΩ/100 kΩ,
Code = 0x40
600/100/40
kHz
Total Harmonic Distortion
THDW
VA =1 V rms, f = 1 kHz, RAB = 10 kΩ
0.05
%
VW Settling Time (10 kΩ/50 kΩ/100 kΩ)
tS
VA = 5 V ±1 LSB Error Band
2
µs
Resistor Noise Voltage Density
eN_WB
RWB = 5 kΩ, RS = 0
9
nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VA = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A and W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = 5 V.




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