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ADS5272IPFP Arkusz danych(PDF) 9 Page - Burr-Brown (TI) |
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ADS5272IPFP Arkusz danych(HTML) 9 Page - Burr-Brown (TI) |
9 / 16 page ADS5272 SBAS324 − JUNE 2004 www.ti.com 9 PIN DESCRIPTIONS NAME PIN # NUMBER OF PINS I/O DESCRIPTION AVDD 1, 7, 14, 47, 54, 60, 63, 70, 75 9 I Analog Power Supply AVSS 4, 8, 11, 50, 53, 57, 61, 62, 68, 72-74, 79, 80 14 I Analog Ground LVDD 25, 35 2 I LVDS Power Supply LVSS 15, 17, 18, 26, 36, 43, 44, 46 8 I LVDS Ground IN1P 2 1 I Channel 1 Differential Analog Input High IN1N 3 1 I Channel 1 Differential Analog Input Low IN2P 5 1 I Channel 2 Differential Analog Input High IN2N 6 1 I Channel 2 Differential Analog Input Low IN3P 9 1 I Channel 3 Differential Analog Input High IN3N 10 1 I Channel 3 Differential Analog Input Low IN4P 12 1 I Channel 4 Differential Analog Input High IN4N 13 1 I Channel 4 Differential Analog Input Low IN5P 48 1 I Channel 5 Differential Analog Input High IN5N 49 1 I Channel 5 Differential Analog Input Low IN6P 51 1 I Channel 6 Differential Analog Input High IN6N 52 1 I Channel 6 Differential Analog Input Low IN7P 55 1 I Channel 7 Differential Analog Input High IN7N 56 1 I Channel 7 Differential Analog Input Low IN8P 58 1 I Channel 8 Differential Analog Input High IN8N 59 1 I Channel 8 Differential Analog Input Low REFT 67 1 I/O Reference Top Voltage (0.1 µF capacitor to ground) REFB 66 1 I/O Reference Bottom Voltage (0.1 µF capacitor to ground) VCM 65 1 O Common-Mode Output Voltage INT/EXT 69 1 I Internal/External Reference Select; 0 = External, 1 = Internal PD 16 1 I Power-Down; 0 = Normal, 1 = Power-Down LCLKP 19 1 O Positive LVDS Clock LCLKN 20 1 O Negative LVDS Clock ADCLK 71 1 I Data Converter Clock Input OUT1P 21 1 O Channel 1 Positive LVDS Data Output OUT1N 22 1 O Channel 1 Negative LVDS Data Output OUT2P 23 1 O Channel 2 Positive LVDS Data Output OUT2N 24 1 O Channel 2 Negative LVDS Data Output OUT3P 27 1 O Channel 3 Positive LVDS Data Output OUT3N 28 1 O Channel 3 Negative LVDS Data Output OUT4P 29 1 O Channel 4 Positive LVDS Data Output OUT4N 30 1 O Channel 4 Negative LVDS Data Output OUT5P 31 1 O Channel 5 Positive LVDS Data Output OUT5N 32 1 O Channel 5 Negative LVDS Data Output OUT6P 33 1 O Channel 6 Positive LVDS Data Output OUT6N 34 1 O Channel 6 Negative LVDS Data Output OUT7P 37 1 O Channel 7 Positive LVDS Data Output OUT7N 38 1 O Channel 7 Negative LVDS Data Output OUT8P 39 1 O Channel 8 Positive LVDS Data Output OUT8N 40 1 O Channel 8 Negative LVDS Data Output ADCLKP 41 1 O Positive LVDS ADC Clock Output ADCLKN 42 1 O Negative LVDS ADC Clock Output ISET 64 1 I/O Bias Current Setting Resistor of 56k Ω to Ground RESET 45 1 I Reset to Default; 0 = Reset, 1 = Normal CS 76 1 I Chip Select; 0 = Select, 1 = No Select SDA 77 1 I Serial Data Input SCLK 78 1 I Serial Data Clock |
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