ST78C36/36A

áç

áç

áç

áç

ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO

REV. 5.0.1

6

2.0

STANDARD DEFINITIONS

s

Compatible Mode: “Centronics” or standard mode.

s

Nibble mode: 4 bits at a time using status lines for data “Hewlett Packard Bi-tronics”.

s

EPP: Enhanced Parallel port-used primarily by non-printer peripherals.

s

ECP: Extended Capability Port-used primarily by new generation of printers and scanners.

3.0

INTERNAL REGISTERS

3.1

DATA REGISTER (DATA )

DATA Bits 7-0:

For host output cycles in SPP mode (ECR mode 000) or PS/2 mode (ECR mode 001), data from the host is

registered at the trailing edge of -IOW. On host input cycles, data at the peripheral port is passed through to

the host data bus.

3.2

ECP FIFO ADDRESS ( ECP-AFIFO )

ECP-AFIFO Bits 7-0:

This port is only available for programmed I/O (non-DMA), and only has significance for host write. Data

written to this port is stored in the FIFO if FIFO-F = 0 and will be lost if FIFO-F = 1. A 9th FIFO bit (tag) is set

low on write. A read from this port is the same as a read at 400.

3.3

STATUS REGISTER ( DSR )

This status register is read-only except for bit-0, and all bits are latched for the duration of -IOR.

DSR Bit-0:

If EPP mode is not selected, this bit returns logic one. During EPP mode, bit-0 will return a high if the EPP 10

msecond TimeOut elapsed during the last EPP read or write cycle (this TimeOut also aborts the EPP cycle).

This status bit is cleared by exiting EPP mode or by the host writing a high to bit-0 of this register.

DSR Bits 2-1:

Reserved, logic one.

DSR Bit-3:

The true state of the -ERROR pad.

DSR Bit-4:

The true state of the SLCT pad.

DSR Bit-5:

The true state of the PE(mpty) pad.

DSR Bit-6:

The true state of the -ACK pad.

DSR Bit-7:

The complement of the BUSY pad.

3.4

CONTROL REGISTER ( DCR )

DCR Bit-0:

The complement of this bit drives -STROBE, and the complement of the pad state is returned for read.