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AD6636BBCZ1 Arkusz danych(PDF) 2 Page - Analog Devices |
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AD6636BBCZ1 Arkusz danych(HTML) 2 Page - Analog Devices |
2 / 72 page AD6636 Rev. 0 | Page 2 of 72 TABLE OF CONTENTS Product Description ......................................................................... 3 Product Highlights ....................................................................... 4 Specifications..................................................................................... 5 Electrical Characteristics ............................................................. 5 General Timing Characteristics ................................................. 6 Microport Timing Characteristics ............................................. 7 Serial Port Timing Characteristics ............................................. 8 Explanation of Test Levels for Specifications............................ 8 Absolute Maximum Ratings............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Pin Listing for Power, Ground, Data and Address Buses ...... 12 Timing Diagrams............................................................................ 13 Theory of Operation ...................................................................... 19 ADC Input Port .......................................................................... 19 PLL Clock Multiplier ................................................................. 20 ADC Gain Control ..................................................................... 21 ADC Input Port Monitor Function.......................................... 22 Quadrature I/Q Correction Block............................................ 24 Input Crossbar Matrix ............................................................... 26 Numerically Controlled Oscillator (NCO) ............................. 26 Fifth-Order CIC Filter ............................................................... 28 FIR Half-Band Block.................................................................. 29 Intermediate Data Router ......................................................... 32 Mono-Rate RAM Coefficient Filter (MRCF) ......................... 32 Decimating RAM Coefficient Filter (DRCF) ........................ 33 Channel RAM Coefficient Filter (CRCF) ............................... 35 Interpolating Half-Band Filter.................................................. 36 Output Data Router ................................................................... 37 Automatic Gain Control............................................................ 39 Parallel Port Output ................................................................... 43 User-Configurable Built-In Self-Test (BIST) .......................... 47 Chip Synchronization ................................................................ 47 Serial Port Control ..................................................................... 48 Microport .................................................................................... 52 JTAG Boundary Scan................................................................. 53 Memory Map .................................................................................. 54 Reading the Memory Map Table.............................................. 54 Global Register Map .................................................................. 56 Input Port Register Map ............................................................ 59 Channel Register Map ............................................................... 62 Output Port Register Map ......................................................... 67 Design Notes ................................................................................... 70 Outline Dimensions ....................................................................... 72 Ordering Guide .......................................................................... 72 REVISION HISTORY 8/04—Revision 0: Initial Version |
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