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CX72301-11 Arkusz danych(PDF) 8 Page - List of Unclassifed Manufacturers |
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8 / 20 page DATA SHEET • CX72301 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 8 July 21, 2004 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 101090H Modulation data samples in the Modulation Data Register can be from 2 to 12 bits long, and enable the user to select how many distinct frequency steps are to be used for the desired modulation scheme. The user can also control the frequency deviation through the modulation data magnitude offset in the Modulation Control Register. This allows shifting of the modulation data to accomplish a 2m multiplication of frequency deviation. NOTE: The programmable range of –0.5 to +0.5 of the main ∆Σ modulator can be exceeded up to the condition where the sum of the dividend and the modulation data conform to the following relationship: -0.5625 N mod dividend + 0.5625 When the sum of the dividend and modulation data lie outside this range, the value of Ninteger must be changed. For a more detailed description of direct digital modulation functionality, refer to the Skyworks Application Note, Direct Digital Modulation Using the CX72300, CX72301, and CX72302 Dual Synthesizers/PLLs (document number 101349). Register Descriptions This section describes the CX72301 registers. All register writes are programmed address first, followed directly with data. MSBs are entered first. On power-up, all registers are reset to 0x000 except registers at address 0x0 and 0x3, which are set to 0x006. Table 1 provides a description for each of the CX72301 device registers. For more information on register loading, refer to the Synthesizer Register Programming section in this document. Synthesizer Registers Main Synthesizer Registers. The Main Divider Register contains the integer portion closest to the desired fractional-N (or the integer-N) value minus 32 for the main synthesizer. This register, in conjunction with the Main Dividend Registers (which control the fraction offset from –0.5 to +0.5), allows selection of a precise frequency. As shown in Figure 6, the value to be loaded is: • Main Synthesizer Divider Index = 9-bit value for the integer portion of the main synthesizer dividers. Valid values for this register are from 6 to 505 (fractional-N) or 0 to 511 (integer-N). The Main Dividend MSB and LSB Registers control the fraction part of the desired fractional-N value and allow an offset of –0.5 to + 0.5 to the main integer selected through the Main Divider Register. As shown in Figures 7 and 8, values to be loaded are: • Main Synthesizer Dividend (MSBs) = 10-bit value for the MSBs of the 18-bit dividend for the main synthesizer. • Main Synthesizer Dividend (LSBs) = 8-bit value for the LSBs of the 18-bit dividend for the main synthesizer. The Main Dividend MSB and LSB Register values are 2's complement format. NOTE: When in 10-bit mode, the Main Synthesizer Dividend (LSBs) is not required. For information on programming and loading order for these registers, see the Operation section of this document. Table 1. CX72301 Register Map Address (Hex) Register (Note 1) Length (Bits) Address (Bits) 0 Main Divider Register 12 4 1 Main Dividend MSB Register 12 4 2 Main Dividend LSB Register 12 4 3 Auxiliary Divider Register 12 4 4 Auxiliary Dividend Register 12 4 5 Reference Frequency Dividers Register 12 4 6 Control Register—phase detector/charge pumps 12 4 7 Control Register—power down/multiplexer output select 12 4 8 Modulation Control Register 12 4 9 — Modulation Data Register Modulation Data Register (Note 2) — direct input 12 2 ≤ length ≤ 12 bits 4 0 Note 1: All registers are write only. Note 2: No address bits are required for modulation data. Any serial data between 2 and 12 bits long is considered modulation data. |
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